Invention Grant
- Patent Title: JFET having width defined by trench isolation
- Patent Title (中): JFET具有由沟槽隔离限定的宽度
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Application No.: US13597439Application Date: 2012-08-29
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Publication No.: US09076760B2Publication Date: 2015-07-07
- Inventor: Binghua Hu , Pinghai Hao , Sameer Pendharkar
- Applicant: Binghua Hu , Pinghai Hao , Sameer Pendharkar
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank Cimino
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H01L29/417 ; H01L21/00 ; H01L29/423 ; H01L29/808 ; H01L29/06 ; H01L29/10

Abstract:
A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.
Public/Granted literature
- US20140062524A1 JFET HAVING WIDTH DEFINED BY TRENCH ISOLATION Public/Granted day:2014-03-06
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