Invention Grant
US09129071B2 Coherence controller slot architecture allowing zero latency write commit
有权
相干控制器插槽架构允许零延迟写入提交
- Patent Title: Coherence controller slot architecture allowing zero latency write commit
- Patent Title (中): 相干控制器插槽架构允许零延迟写入提交
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Application No.: US14057205Application Date: 2013-10-18
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Publication No.: US09129071B2Publication Date: 2015-09-08
- Inventor: Matthew D Pierson , Kai Chirca , Timothy D Anderson
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frank D. Cimino
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F13/42 ; G06F13/16 ; H04L29/06

Abstract:
This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this data will be available earlier than if the memory controller stalled this write pending snoop responses. This invention computes write enable strobes for the coherence write data based upon the cache dirty tags. This invention initiates a snoop cycle based upon the address of the coherence write. The stored write enable strobes enable determination of which data to write to the endpoint memory upon a cached and dirty snoop response.
Public/Granted literature
- US20140115271A1 COHERENCE CONTROLLER SLOT ARCHITECTURE ALLOWING ZERO LATENCY WRITE COMMIT Public/Granted day:2014-04-24
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