Invention Grant
- Patent Title: Flip chip interconnection having narrow interconnection sites on the substrate
- Patent Title (中): 倒装芯片互连在基板上具有窄的互连点
-
Application No.: US13645397Application Date: 2012-10-04
-
Publication No.: US09159665B2Publication Date: 2015-10-13
- Inventor: Rajendra D. Pendse
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/60
- IPC: H01L21/60 ; H01L23/488 ; H01L23/498 ; H01L21/56 ; H01L23/00 ; H05K1/11 ; H05K3/34

Abstract:
A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.
Public/Granted literature
- US20130026628A1 Flip Chip Interconnection having Narrow Interconnection Sites on the Substrate Public/Granted day:2013-01-31
Information query
IPC分类: