Invention Grant
- Patent Title: Fail safe circuit
- Patent Title (中): 故障安全电路
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Application No.: US14199453Application Date: 2014-03-06
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Publication No.: US09209718B2Publication Date: 2015-12-08
- Inventor: Andrew Jeremy Sykes , Richard Mark Wain , Colin Hargis
- Applicant: Control Techniques Limited
- Applicant Address: GB Newtown
- Assignee: CONTROL TECHNIQUES LIMITED
- Current Assignee: CONTROL TECHNIQUES LIMITED
- Current Assignee Address: GB Newtown
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: GB1304187.6 20130308
- Main IPC: H03K19/00
- IPC: H03K19/00 ; H02P3/22 ; H02P3/02 ; H02H3/24 ; H02H7/08 ; H02M1/32 ; H02M7/5387 ; H02M1/00

Abstract:
Apparatus for preventing output of an input signal is disclosed. The apparatus comprises a signal control unit comprising a signal buffering unit having an input and an output, the signal buffering unit arranged to receive an input signal and pass the input signal to the output when the signal buffering unit is powered, wherein a negative power supply terminal of the signal buffering unit is arranged to be supplied by a first power source having a voltage. The signal control unit also comprises a boost circuit arranged to boost the voltage of the first power source to a boosted voltage higher than the voltage of the first power source and supply either the voltage of the first power source or the boosted voltage to a positive power supply terminal of the signal buffering unit. The signal buffering unit is powered when the boosted voltage is supplied to the positive power supply terminal of the signal buffering unit and the signal buffering unit is not powered when voltage of the first power supply terminal is supplied to the positive power supply terminal of the signal buffering unit. Also disclosed is an apparatus for providing output voltages for driving a motor as well as a motor drive system.
Public/Granted literature
- US20140253008A1 Fail Safe Circuit Public/Granted day:2014-09-11
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