Invention Grant
US09219480B2 Low tau synchronizer flip-flop with dual loop feedback approach to improve mean time between failure
有权
低同步触发器采用双回路反馈方式,提高故障间的平均时间
- Patent Title: Low tau synchronizer flip-flop with dual loop feedback approach to improve mean time between failure
- Patent Title (中): 低同步触发器采用双回路反馈方式,提高故障间的平均时间
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Application No.: US14170342Application Date: 2014-01-31
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Publication No.: US09219480B2Publication Date: 2015-12-22
- Inventor: Hwong-Kwo Lin , Ge Yang , Xi Zhang , Ying Huang
- Applicant: Nvidia Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Nvidia Corporation
- Current Assignee: Nvidia Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H03K19/003 ; H03K3/037 ; G06F1/10

Abstract:
A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).
Public/Granted literature
- US20150222266A1 LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO IMPROVE MEAN TIME BETWEEN FAILURE Public/Granted day:2015-08-06
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