公开(公告)号：US09525401B2

公开(公告)日：2016-12-20

申请号：US14644637

申请日：2015-03-11

申请人： NVIDIA Corporation

发明人： Xi Zhang ,  Hwong-Kwo Lin ,  Ge Yang ,  Lingfei Deng

IPC分类号： H03K3/00 ,  H03K3/012 ,  H03K3/037 ,  H03K19/21

CPC分类号： H03K3/012 ,  G01R31/318541 ,  H03K3/0372 ,  H03K19/21

摘要： Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

摘要翻译： 低时钟电源触发器。 根据本发明的第一实施例，触发器电子电路包括以触发器配置耦合到从锁存器的主锁存器。 触发器电子电路还包括用于将输入与主锁存器的输入与从锁存器的输出进行比较的时钟控制电路，并且响应于比较，当触发器电路电路将时钟信号阻塞到主锁存器和从锁存器时， 触发器电子电路处于静止状态。

公开(公告)号：US09183922B2

公开(公告)日：2015-11-10

申请号：US13901614

申请日：2013-05-24

申请人： NVIDIA Corporation

发明人： Jun Yang ,  Hwong-Kwo Lin ,  Ju Shen ,  Yong Li ,  Hua Chen

IPC分类号： G11C11/00 ,  G11C11/412 ,  G11C11/419

CPC分类号： G11C11/412 ,  G11C11/419

摘要： Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch.

摘要翻译： 公开了根据一个或多个实施例的与八晶体管（8T）静态随机存取存储器（SRAM）单元相关的器件，系统和/或方法。 在一个实施例中，公开了一种SRAM存储单元，其包括字线，写列选择线，交叉耦合数据锁存器和串联耦合到第二NMOS开关器件的第一NMOS开关器件。 在该实施例中，第一NMOS开关器件的栅极节点耦合到字线，第一NMOS开关器件的源节点耦合到交叉耦合数据锁存器，第二NMOS开关器件的栅极节点被耦合 到写列选择线，并且第二NMOS开关器件的源节点耦合到交叉耦合数据锁存器。

公开(公告)号：US08988123B2

公开(公告)日：2015-03-24

申请号：US13715969

申请日：2012-12-14

申请人： NVIDIA Corporation

发明人： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu

IPC分类号： H03K3/289 ,  H03K3/037

CPC分类号： H03K3/0375

摘要： Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.

摘要翻译： 小区域低功率数据保留触发器。 根据本发明的第一实施例，电路包括耦合到数据保持锁存器的主锁存器。 数据保持锁存器被配置为作为从锁存器操作到主锁存器，以在正常操作期间实现主从触发器。 数据保持锁存器配置为在主器件锁存器掉电时，在低功耗数据保持模式期间保持主从触发器的输出值。 单个控制输入被配置为在正常操作和低功率数据保持模式之间进行选择。 电路可以独立于第三锁存器。

公开(公告)号：US20140129887A1

公开(公告)日：2014-05-08

申请号：US13668143

申请日：2012-11-02

申请人： NVIDIA CORPORATION

发明人： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC分类号： G01R31/3177

CPC分类号： G01R31/318541 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318594

摘要： A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

摘要翻译： 扫描触发电路包括扫描输入子电路和选择子电路。 扫描输入子电路被配置为接收扫描输入信号和扫描使能信号，并且当扫描使能信号被激活时，产生表示相对于时钟输入的转变而被延迟的扫描输入信号的互补扫描输入信号 信号在两个不同的逻辑电平之间。 选择子电路耦合到扫描输入子电路并且被配置为接收互补扫描输入信号，并且基于扫描使能信号，将扫描输入信号或数据信号的反相形式输出为第一选择 输入信号。

公开(公告)号：US10672461B2

公开(公告)日：2020-06-02

申请号：US14160706

申请日：2014-01-22

申请人： Nvidia Corporation

发明人： Haiyan Gong ,  Lei Wang ,  Sing-Rong Li ,  Hwong-Kwo Lin ,  Pai-Yi Chang

IPC分类号： G11C11/419 ,  G11C7/12

摘要： A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.

公开(公告)号：US09542992B2

公开(公告)日：2017-01-10

申请号：US13865281

申请日：2013-04-18

申请人： NVIDIA CORPORATION

发明人： Hwong-Kwo Lin ,  Ge Yang ,  Fei Song ,  Xi Zhang ,  Haiyan Gong

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.

摘要翻译： 静态随机存取存储器（SRAM）单元包括被配置为在存储节点中存储数据位的存储单元。 SRAM单元还包括耦合到存储单元的存取单元。 访问单元被配置为当字线被断言时将电流传送到存储节点。 SRAM单元进一步包括行标头，其被配置为当字线未被断言时提供来自电源的电流，并且当字线被断言时不提供来自电源的电流。 SRAM单元进一步包括列头，其配置成当写入列线未被置位时提供来自电源的电流，并且当写入列线被断言时不提供来自电源的电流。

公开(公告)号：US09355710B2

公开(公告)日：2016-05-31

申请号：US14162639

申请日：2014-01-23

申请人： Nvidia Corporation

发明人： Haiyan Gong ,  Lei Wang ,  Sing-Rong Li ,  Hwong-Kwo Lin ,  Pai-Yi Chang

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C5/14

CPC分类号： G11C11/419 ,  G11C5/147

摘要： A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.

摘要翻译： 混合写入辅助存储器系统包括阵列电压源和由位线和字线控制的静态随机存取存储器（SRAM）单元，并采用耦合到阵列电压源的可分离单元电源电压。 此外，混合写入辅助存储器系统包括耦合到SRAM单元的电源电压下降单元，并且在写入操作期间提供可分离单元电源电压的电压降低。 此外，混合写辅助存储器系统包括负位线单元，其耦合到电源电压下降单元，并且在写操作期间与可分离单元电源电压的电压降低同时提供负位线电压。 还提供了一种操作混合写入辅助存储器系统的方法。

公开(公告)号：US09123438B2

公开(公告)日：2015-09-01

申请号：US14054313

申请日：2013-10-15

申请人： Nvidia Corporation

发明人： Hwong-Kwo Lin ,  Lei Wang ,  Spencer Gold ,  Zhenye Jiang

IPC分类号： G11C7/22 ,  G11C11/419 ,  G11C11/4076

CPC分类号： G11C11/419 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/417 ,  G11C29/022 ,  G11C29/028

摘要： A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.

摘要翻译： 可配置的延迟电路和时钟缓冲的方法。 可配置延迟电路的一个实施例包括：（1）与第二延迟级串联电耦合的第一延迟级，第一延迟级和第二延迟级各自具有电耦合到信号源的输入端，以及（2 ）电耦合在所述第一延迟级和所述第二延迟级之间的延迟路径选择电路，并且可操作以在包括所述第一延迟级的延迟路径和包括所述第一延迟级和所述第二延迟级的另一延迟路径之间进行选择。

公开(公告)号：US09110141B2

公开(公告)日：2015-08-18

申请号：US13668143

申请日：2012-11-02

申请人： NVIDIA Corporation

发明人： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318541 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318594

摘要： A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

摘要翻译： 扫描触发电路包括扫描输入子电路和选择子电路。 扫描输入子电路被配置为接收扫描输入信号和扫描使能信号，并且当扫描使能信号被激活时，产生表示相对于时钟输入的转变而被延迟的扫描输入信号的互补扫描输入信号 信号在两个不同的逻辑电平之间。 选择子电路耦合到扫描输入子电路并且被配置为接收互补扫描输入信号，并且基于扫描使能信号，将扫描输入信号或数据信号的反相版本输出为第一选择 输入信号。

公开(公告)号：US09484115B1

公开(公告)日：2016-11-01

申请号：US14711712

申请日：2015-05-13

申请人： NVIDIA CORPORATION

发明人： Stephen Felix ,  Hwong-Kwo Lin ,  Spencer Gold ,  Jing Guo ,  Andreas Gotterba ,  Jason Golbus ,  Karthik Natarajan ,  Jun Yang ,  Zhenye Jiang ,  Ge Yang ,  Lei Wang ,  Yong Li ,  Hua Chen ,  Haiyan Gong ,  Beibei Ren ,  Eric Voelkel

IPC分类号： G11C29/08 ,  G11C11/16 ,  G11C7/00 ,  G11C5/14

CPC分类号： G11C11/1697 ,  G11C5/143 ,  G11C7/00 ,  G11C11/417 ,  G11C29/08 ,  G11C2207/2227

摘要： A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

摘要翻译： 被配置为选择对静态随机存取存储器单元的电源的子系统将专用存储器电源电压的电平与主系统电源电压进行比较。 当系统电压高于具有一定余量的存储器电源电压时，子系统将主系统电源切换到SRAM单元。 当系统电压低于存储器电源电压时，子系统将存储器电源切换到SRAM单元。 当系统电压与存储器电源相当时，如果性能是优先考虑的话，子系统将系统电压切换到SRAM单元，但如果降低功耗是优先考虑的话，将存储器电源切换到SRAM单元。 以这种方式，系统实现最佳性能而不会导致稳态功率损耗，并避免访问存储器时的定时问题。