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1.发明申请LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO IMPROVE MEAN TIME BETWEEN FAILURE 有权低双向同步旋转双向反馈方法提高故障时间之间的平均时间公开(公告)号：US20150222266A1
公开(公告)日：2015-08-06
申请号：US14170342
申请日：2014-01-31
Applicant: Nvidia Corporation
Inventor： Hwong-Kwo Lin , Ge Yang , Xi Zhang , Ying Huang
IPC: H03K19/003 , G06F1/10 , H03K3/037
CPC classification number: H03K19/003 , G06F1/10 , H03K3/0372
Abstract: A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).
Abstract translation: 触发器和从异步域接收数字信号的方法。 在一个实施例中，触发器包括：（1）耦合到触发器输入并具有第一和第二稳定状态的第一环路和（2）耦合到第一环路并具有第一和第二稳定状态的第二环路 在第一和第二回路中的交叉耦合的反相器的特性产生亚稳态，其在第一回路中朝向第一稳定状态倾斜，并且朝向第二回路中的第二稳定状态倾斜。 触发器的某些实施例具有较低的时间常数，因此具有较高的平均故障间隔时间（MTBF）。
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2.发明授权Low tau synchronizer flip-flop with dual loop feedback approach to improve mean time between failure 有权低同步触发器采用双回路反馈方式，提高故障间的平均时间公开(公告)号：US09219480B2
公开(公告)日：2015-12-22
申请号：US14170342
申请日：2014-01-31
Applicant: Nvidia Corporation
Inventor： Hwong-Kwo Lin , Ge Yang , Xi Zhang , Ying Huang
IPC: H03K3/00 , H03K19/003 , H03K3/037 , G06F1/10
CPC classification number: H03K19/003 , G06F1/10 , H03K3/0372
Abstract: A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).
Abstract translation: 触发器和从异步域接收数字信号的方法。 在一个实施例中，触发器包括：（1）耦合到触发器输入并具有第一和第二稳定状态的第一环路和（2）耦合到第一环路并具有第一和第二稳定状态的第二环路 在第一和第二回路中的交叉耦合的反相器的特性产生亚稳态，其在第一回路中朝向第一稳定状态倾斜，并且朝向第二回路中的第二稳定状态倾斜。 触发器的某些实施例具有较低的时间常数，因此具有较高的平均故障间隔时间（MTBF）。
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