An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a separate aging path with driving and receiving flip flops (FFs) and a tunable replica circuit (TRC) to enable measurements of single-transition DC-stressed path delay that only propagates through stressed transistors or other circuit element(s). A finite state machine (FSM) in the aging monitor circuit is configured to adjust a frequency of a clock signal output by a digitally controlled oscillator (DCO) in response to an error signal output by the receiving FF. The error signal is generated in response to single-transition DC-stressed path delay; and therefore enables the adjustment of the frequency of the dock signal to correspond to an amount or effect of the delay.