Invention Grant
US09231585B2 System and method for calibrating chips in a 3D chip stack architecture
有权
用于在3D芯片堆栈架构中校准芯片的系统和方法
- Patent Title: System and method for calibrating chips in a 3D chip stack architecture
- Patent Title (中): 用于在3D芯片堆栈架构中校准芯片的系统和方法
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Application No.: US14489508Application Date: 2014-09-18
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Publication No.: US09231585B2Publication Date: 2016-01-05
- Inventor: Ying-Yu Hsu , Ruey-Bin Sheen , Chih-Hsien Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G01R31/02
- IPC: G01R31/02 ; H03K17/94 ; H01L25/065 ; G01R31/26 ; G01R31/30 ; G01R31/319 ; G01R31/3193 ; H01L25/18
Abstract:
A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.
Public/Granted literature
- US20150002194A1 SYSTEM AND METHOD FOR CALIBRATING CHIPS IN A 3D CHIP STACK ARCHITECTURE Public/Granted day:2015-01-01
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