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    Full range realignment ring oscillator
    4.
    发明授权
    Full range realignment ring oscillator 有权

    公开(公告)号：US10461723B2

    公开(公告)日：2019-10-29

    申请号：US15826910

    申请日：2017-11-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsien Tsai ,  Chen-Hsiang Hsieh ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

    IPC: H03K3/03 ,  H03K3/356 ,  H03L7/081 ,  H03L7/087 ,  H03L7/099

    Abstract: A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate. A drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are electrically connected to each other and are further electrically connected to a second input of the OR gate and a second input of the AND gate.

    3D IC with serial gate MOS device, and method of making the 3D IC
    6.
    发明授权
    3D IC with serial gate MOS device, and method of making the 3D IC 有权
    具有串行栅极MOS器件的3D IC和制造3D IC的方法

    公开(公告)号：US09035464B2

    公开(公告)日：2015-05-19

    申请号：US14014472

    申请日：2013-08-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao Chieh Li ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

    IPC: H01L29/04 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/481 ,  H01L21/76805 ,  H01L23/5226 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.

    Abstract translation: 芯片堆叠包括具有至少第一器件的第一集成电路（IC）管芯，该第一器件包括在第一源极和第一漏极之间的第一沟道区域之上的第一源极，第一漏极和第一栅极电极。 第二IC管芯具有至少第二器件，其包括在第二源极和第二漏极之间的第二沟道区域上方的第二源极，第二漏极和第二栅极电极。 第二栅电极通过包括第一贯穿衬底通孔（TSV）的路径连接到第一栅电极，第二漏极通过包括第二TSV的路径连接到第一源极。

    Optimized layout cell
    7.
    发明授权
    Optimized layout cell 有权

    公开(公告)号：US11681852B2

    公开(公告)日：2023-06-20

    申请号：US17672137

    申请日：2022-02-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ruey-Bin Sheen ,  Tien-Chien Huang ,  Chuan-Yao Tan

    IPC: G06F30/398 ,  G06F30/392 ,  G06F30/3953

    CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/3953

    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

    Ring oscillator, controlling circuit and methods for realignment
    9.
    发明授权
    Ring oscillator, controlling circuit and methods for realignment 有权

    公开(公告)号：US10516385B2

    公开(公告)日：2019-12-24

    申请号：US15475258

    申请日：2017-03-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsien Tsai ,  Ruey-Bin Sheen ,  Chih-Hsien Chang ,  Cheng-Hsiang Hsieh

    IPC: H03K3/03

    Abstract: A ring oscillator is provided. The ring oscillator includes a pseudo pass-gate inverter, a third transistor, a fourth transistor and a delay chain. The pseudo pass-gate inverter includes a first transistor and a second transistor in series. The third transistor is connected in series with the pseudo pass-gate inverter. The drain of the fourth transistor is connected to an output of the pseudo pass-gate inverter. The gate of the fourth transistor is connected to the gate of the third transistor to receive the realignment signal. The delay chain includes a plurality of delay cells. An input of the delay chain is connected to the output of the pseudo pass-gate inverter. When the realignment signal is in a realignment state, the third transistor is turned off, the fourth transistor is turned on.

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