An apparatus includes a first programmable circuit block including a plurality of programmable circuit elements. The plurality of programmable circuit elements include a hardwired, instrumented memory element. The instrumented memory element includes a first flip-flop configured to receive a data signal, a delay circuit configured to generate a delayed version of the data signal, and a second flip-flop identical to the first flip-flop and configured to receive the delayed version of the data signal. The instrumented memory element also may include a comparator configured to compare an output signal from the first flip-flop and an output signal from the second flip-flop and an error signal generator. The error signal generator is configured to generate an error signal responsive to a mismatch of bits between the output signal from the first flip-flop and the output signal from the second flip-flop.