Invention Grant
US09235528B2 Write endurance management techniques in the logic layer of a stacked memory
有权
在堆叠式存储器的逻辑层中写入耐力管理技术
- Patent Title: Write endurance management techniques in the logic layer of a stacked memory
- Patent Title (中): 在堆叠式存储器的逻辑层中写入耐力管理技术
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Application No.: US13725305Application Date: 2012-12-21
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Publication No.: US09235528B2Publication Date: 2016-01-12
- Inventor: Lisa R. Hsu , Gabriel H. Loh , Michael Ignatowski , Michael J. Schulte , Nuwan S. Jayasena , James M. O'Connor
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Volpe and Koenig, P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F12/10 ; G06F11/20 ; G06F11/16

Abstract:
A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.
Public/Granted literature
- US20140181457A1 Write Endurance Management Techniques in the Logic Layer of a Stacked Memory Public/Granted day:2014-06-26
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