公开(公告)号：US11762828B2

公开(公告)日：2023-09-19

申请号：US16104662

申请日：2018-08-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  Nuwan S. Jayasena

IPC: G06F16/00 ,  G06F16/22

CPC classification number: G06F16/2255

Abstract: A method includes, for each key of a plurality of keys, identifying from a set of buckets a first bucket for the key based on a first hash function, and identifying from the set of buckets a second bucket for the key based on a second hash function. An entry for the key is stored in a bucket selected from one of the first bucket and the second bucket. The entry is inserted in a sequence of entries in a memory block. A position of the entry in the sequence of entries corresponds to the selected bucket. For each bucket in the set of buckets, an indication of a number of entries in the bucket is recorded.

公开(公告)号：US10705972B2

公开(公告)日：2020-07-07

申请号：US15264400

申请日：2016-09-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini-Farahani ,  Alexander D. Breslow ,  Nuwan S. Jayasena

IPC: G06F12/00 ,  G06F12/1009 ,  G06F13/16 ,  G06F13/00

Abstract: Systems, apparatuses, and methods for determining preferred memory page management policies by software are disclosed. Software executing on one or more processing units generates a memory request. Software determines the preferred page management policy for the memory request based at least in part on the data access size and data access pattern of the memory request. Software conveys an indication of a preferred page management policy to a memory controller. Then, the memory controller accesses memory for the memory request using the preferred page management policy specified by software.

公开(公告)号：US10522193B2

公开(公告)日：2019-12-31

申请号：US16129252

申请日：2018-09-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  Bradford M. Beckmann ,  James M. O'Connor ,  Lisa R. Hsu

IPC: G06F12/00 ,  G11C5/06 ,  G06F12/02 ,  G06F12/10 ,  G06F13/16 ,  G11C7/10

Abstract: A system, method, and computer program product are provided for a memory device system. One or more memory dies and at least one logic die are disposed in a package and communicatively coupled. The logic die comprises a processing device configurable to manage virtual memory and operate in an operating mode. The operating mode is selected from a set of operating modes comprising a slave operating mode and a host operating mode.

公开(公告)号：US10090236B2

公开(公告)日：2018-10-02

申请号：US14995002

申请日：2016-01-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  David A. Roberts

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/15 ,  H01L25/065 ,  H01L25/00

Abstract: The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts.

公开(公告)号：US09804996B2

公开(公告)日：2017-10-31

申请号：US13724506

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： James M. O'Connor ,  Nuwan S. Jayasena ,  Gabriel H. Loh ,  Michael Ignatowski ,  Michael J. Schulte

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/78

CPC classification number: G06F15/7821 ,  Y02D10/12 ,  Y02D10/13

Abstract: Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor.

公开(公告)号：US20170300592A1

公开(公告)日：2017-10-19

申请号：US15438401

申请日：2017-02-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  Dong Ping Zhang ,  Nuwan S. Jayasena

IPC: G06F17/30

CPC classification number: G06F16/9014

Abstract: Methods and mechanisms for managing data in a hash table are disclosed. A computing system includes a hash table configured to store data and hash management logic. In response to receiving a request to insert data into the hash table, the hash management logic is configured to generate a first hash value by applying a first hash function to the key of the key-value pair, and identify a first bucket within the hash table that corresponds to the first hash table. If the first bucket has a slot available, store the key-value pair in the slot. If the first bucket does not have a slot available, select a first slot of the first bucket for conversion to a remap entry, store the key-value pair in a second bucket, and store information associating the key-value pair with the second bucket in the remap entry.

公开(公告)号：US20170212851A1

公开(公告)日：2017-07-27

申请号：US15005378

申请日：2016-01-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Andrew G. Kegel

IPC: G06F13/24

Abstract: The described embodiments include a computing device with multiple interrupt processors for processing interrupts. In the described embodiments, each of the multiple processors is classified as one or more processor types based on factors such as features and functionality of the processor, an operating environment of the processor, the characteristics of some or all of the available interrupts, etc. During operation, an interrupt controller in the computing device receives an indication of an interrupt. The interrupt controller then determines a processor type for processing the interrupt. Next, the interrupt controller causes the interrupt to be processed by one of the plurality of processors that is the determined processor type.

公开(公告)号：US20160124873A1

公开(公告)日：2016-05-05

申请号：US14891523

申请日：2013-05-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yi Xu ,  Nuwan S. Jayasena ,  Yuan Xie

IPC: G06F13/16 ,  G06F1/32 ,  G11C7/10

Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

Abstract translation: 集成电路装置包括可耦合到存储器的存储器控​​制器。 所述存储器控制器基于所述区域特有的存储器定时参数来调度对所述存储器的区域的存储器访问。 一种方法包括在存储器设备处接收存储器访问请求。 该方法还包括从存储器设备的定时数据存储器访问表示存储器定时参数的特定于存储器访问请求所针对的存储器单元电路区域的数据。 该方法还包括在存储器控制器的基础上调度存储器访问请求。

公开(公告)号：US09251069B2

公开(公告)日：2016-02-02

申请号：US14055869

申请日：2013-10-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Gabriel H. Loh ,  Mauricio Breternitz ,  James M. O'Connor ,  Srilatha Manne ,  Nuwan S. Jayasena ,  Mithuna S. Thottethodi

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0848 ,  G06F12/0888 ,  G06F12/0897 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，其中第一存储体断电。 作为响应，向第二存储体写入请求以指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。 如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。 如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。 高速缓存控制器将这些数据写入较低级别的内存。

公开(公告)号：US20150198991A1

公开(公告)日：2015-07-16

申请号：US14152826

申请日：2014-01-10

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Bircher ,  Madhu Saravana Sibi Govindan ,  Manish Arora ,  Michael J. Schulte ,  Nuwan S. Jayasena

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D50/20

Abstract: Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

Abstract translation: 电源管理状态的持续时间是以每个进程为基础预测的。 一些实施例包括在与一个或多个进程相关联的一个或多个数据结构中存储指示与进程相关联的电力管理状态的先前持续时间的信息。 一些实施例还包括使用存储在数据结构中的信息来预测过程的功率管理状态的后续持续时间。