公开(公告)号：US09910605B2

公开(公告)日：2018-03-06

申请号：US15353431

申请日：2016-11-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/0811

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

公开(公告)号：US20160062803A1

公开(公告)日：2016-03-03

申请号：US14935056

申请日：2015-11-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/50 ,  G06F12/08

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.

Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制在从一组表中选择的表中执行查找以从资源集合中识别资源。 当资源不可用于执行操作并且直到选择用于执行操作的另一资源为止时，选择机制识别表中的下一个资源，并且当下一个资源可用于执行操作时选择用于执行操作的下一个资源 。

公开(公告)号：US09235528B2

公开(公告)日：2016-01-12

申请号：US13725305

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Lisa R. Hsu ,  Gabriel H. Loh ,  Michael Ignatowski ,  Michael J. Schulte ,  Nuwan S. Jayasena ,  James M. O'Connor

IPC: G06F11/00 ,  G06F12/10 ,  G06F11/20 ,  G06F11/16

CPC classification number: G06F12/10 ,  G06F11/1666 ,  G06F11/2094

Abstract: A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.

Abstract translation: 提供体现本发明的一些方面的用于重新映射外部存储器地址和堆叠存储器中的内部存储器位置的系统，方法和存储器件。 堆叠的存储器包括被配置为存储数据的一个或多个存储器层。 堆叠的存储器还包括连接到存储器层的逻辑层。 逻辑层具有被配置为从外部设备接收读取和写入命令的输入/输出（I / O）端口，被配置为保持外部存储器地址和内部存储器位置之间的关联的存储器映射以及耦合到I / O端口，内存映射和内存层，配置为将从外部设备接收的数据存储到内部存储器位置。

公开(公告)号：US09229803B2

公开(公告)日：2016-01-05

申请号：US13720536

申请日：2012-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Vilas K. Sridharan ,  James M. O'Connor ,  Jaewoong Sim

IPC: G06F11/10 ,  G06F12/08

CPC classification number: G06F11/1064 ,  G06F12/0893

Abstract: A method of managing memory includes installing a first cacheline at a first location in a cache memory and receiving a write request. In response to the write request, the first cacheline is modified in accordance with the write request and marked as dirty. Also in response to the write request, a second cacheline is installed that duplicates the first cacheline, as modified in accordance with the write request, at a second location in the cache memory.

Abstract translation: 管理存储器的方法包括在高速缓冲存储器中的第一位置安装第一高速缓存线并接收写入请求。 响应于写入请求，第一个缓存线根据写入请求进行修改并标记为脏。 还响应于写入请求，安装第二高速缓存线，该第二高速缓存线在高速缓冲存储器的第二位置处复制根据写入请求修改的第一高速缓存线。

公开(公告)号：US09183055B2

公开(公告)日：2015-11-10

申请号：US13761985

申请日：2013-02-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism is configured to perform a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the identified resource is not available for performing the operation and until a resource is selected for performing the operation, the selection mechanism is configured to identify a next resource in the table and select the next resource for performing the operation when the next resource is available for performing the operation.

Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制被配置为在从一组表中选择的表中执行查找，以从资源集合中识别资源。 当所识别的资源不可用于执行操作并且直到选择资源来执行操作时，选择机制被配置为识别表中的下一个资源，并且当下一个资源可用时选择用于执行操作的下一个资源 用于执行操作。

公开(公告)号：US20140372711A1

公开(公告)日：2014-12-18

申请号：US13917033

申请日：2013-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： James M. O'Connor ,  Niladrish Chatterjee ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/161 ,  G06F13/1694

Abstract: A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value.

Abstract translation: 存储器访问代理包括存储器访问生成电路和存储器控制器。 存储器访问生成电路适于以第一有序布置生成多个存储器访问。 存储器控制器耦合到存储器存取产生电路，并且具有输出端口，用于基于存储器访问和外部存储器的特性以第二有序布置提供对输出端口的多个存储器访问。 存储器控制器通过计算有效的行脉冲串值和中断多个行命中请求来基于有效的行脉冲串值来调度行错请求来确定第二排序。

公开(公告)号：US20140181467A1

公开(公告)日：2014-06-26

申请号：US13725063

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Timothy G. Rogers ,  Bradford M. Beckmann ,  James M. O'Connor

IPC: G06F15/80

CPC classification number: G06F9/3887 ,  G06F9/30036

Abstract: Methods, and media, and computer systems are provided. The method includes, the media includes control logic for, and the computer system includes a processor with control logic for overriding an execution mask of SIMD hardware to enable at least one of a plurality of lanes of the SIMD hardware. Overriding the execution mask is responsive to a data parallel computation and a diverged control flow of a workgroup.

Abstract translation: 提供了方法，媒体和计算机系统。 该方法包括：媒体包括用于的控制逻辑，并且计算机系统包括具有用于覆盖SIMD硬件的执行掩码的控制逻辑的处理器，以使能SIMD硬件的多个通道中的至少一个。 覆盖执行掩码响应于数据并行计算和工作组的分散控制流。

公开(公告)号：US20140181414A1

公开(公告)日：2014-06-26

申请号：US14055869

申请日：2013-10-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Gabriel H. Loh ,  Mauricio Breternitz ,  James M. O'Connor ,  Srilatha Manne ,  Nuwan S. Jayasena ,  Mithuna S. Thottethodi

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0848 ,  G06F12/0888 ,  G06F12/0897 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，其中第一存储体断电。 作为响应，向第二组写入请求，指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。 如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。 如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。 高速缓存控制器将这些数据写入较低级别的内存。

公开(公告)号：US20140164708A1

公开(公告)日：2014-06-12

申请号：US13708090

申请日：2012-12-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mauricio Breternitz, JR. ,  James M. O'Connor ,  Srilatha Manne ,  Yasuko Eckert

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0875 ,  G06F12/0891 ,  G06F12/123 ,  Y02D10/13

Abstract: A processor discards spill data from a memory hierarchy in response to the final access to the spill data has been performed by a compiled program executing at the processor. In some embodiments, the final access determined based on a special-purpose load instruction configured for this purpose. In some embodiments the determination is made based on the location of a stack pointer indicating that a method of the executing program has returned, so that data of the returned method that remains in the stack frame is no longer to be accessed. Because the spill data is discarded after the final access, it is not transferred through the memory hierarchy.

Abstract translation: 响应于对处理器执行的编译程序已经执行对溢出数据的最终访问，处理器从存储器层次结构中丢弃溢出数据。 在一些实施例中，基于为此目的配置的专用加载指令确定最终访问。 在一些实施例中，基于指示执行程序的方法已经返回的堆栈指针的位置进行确定，使得保留在堆栈帧中的返回的方法的数据不再被访问。 由于溢出数据在最终访问后被丢弃，因此不会通过内存层次结构传输。

公开(公告)号：US20140149710A1

公开(公告)日：2014-05-29

申请号：US13689421

申请日：2012-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Timothy G. Rogers ,  Bradford M. Beckmann ,  James M. O'Connor

IPC: G06F12/02

CPC classification number: G06F9/3887 ,  G06F9/3851

Abstract: Methods, media, and computing systems are provided. The method includes, the media are configured for, and the computing system includes a processor with control logic for allocating memory for storing a plurality of local register states for work items to be executed in single instruction multiple data hardware and for repacking wavefronts that include work items associated with a program instruction responsive to a conditional statement. The repacking is configured to create repacked wavefronts that include at least one of a wavefront containing work items that all pass the conditional statement and a wavefront containing work items that all fail the conditional statement.

Abstract translation: 提供了方法，媒体和计算系统。 该方法包括：媒体被配置用于计算系统，并且计算系统包括具有控制逻辑的处理器，该控制逻辑用于分配存储器，用于存储要在单指令多数据硬件中执行的工作项的多个本地寄存器状态，以及用于重新包装工作的波前 与响应于条件语句的程序指令相关联的项目。 重新配置被配置为创建重新包装的波前，其包括包含工作项的波前中的至少一个，所述工作项全部通过条件语句，以及包含所有未完成条件语句的工作项的波阵面。