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    Multi-die system performance optimization
    1.
    发明授权
    Multi-die system performance optimization 有权

    公开(公告)号：US11709536B2

    公开(公告)日：2023-07-25

    申请号：US17029852

    申请日：2020-09-23

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Greg Sadowski ,  Sriram Sundaram ,  Stephen Kushnir ,  William C. Brantley ,  Michael J. Schulte

    IPC: G06F1/28 ,  G05F1/625

    CPC classification number: G06F1/28 ,  G05F1/625

    Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

    Die-stacked memory device with reconfigurable logic
    4.
    发明授权
    Die-stacked memory device with reconfigurable logic 有权
    具有可重构逻辑的堆叠式存储器件

    公开(公告)号：US08922243B2

    公开(公告)日：2014-12-30

    申请号：US13726145

    申请日：2012-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nuwan S. Jayasena ,  Michael J. Schulte ,  Gabriel H. Loh ,  Michael Ignatowski

    IPC: H03K19/177 ,  G11C7/00

    CPC classification number: H03K19/1776 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4234 ,  G06F15/7867 ,  G11C7/1006 ,  G11C7/1048 ,  G11C29/70 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H03K19/17776 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.

    Abstract translation: 芯片堆叠的存储器件包括可重构逻辑器件，以在执行各种数据操作操作和使用存储在管芯堆叠的存储器件中的数据的其他存储器操作中提供实现灵活性，或者导致要存储在管芯堆叠存储器件中的数据。 堆叠式存储设备。 代表可重配置逻辑器件的相应逻辑配置的一个或多个配置文件可被存储在管芯堆叠的存储器件的配置存储器中，并且配置控制器可使用所选择的一个存储器件对可重新配置的逻辑器件进行编程 配置文件。 由于逻辑管芯和存储器管芯的集成，与可堆叠存储器件外部的器件相比，可重构逻辑器件可以执行具有更高带宽和更低延迟和功耗的各种数据操作操作。

    Power control for multi-core data processor
    7.
    发明授权
    Power control for multi-core data processor 有权
    多核数据处理器的电源控制

    公开(公告)号：US09360918B2

    公开(公告)日：2016-06-07

    申请号：US13724133

    申请日：2012-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Srilatha Manne ,  Sanjay Pant ,  Youngtaek Kim ,  Michael J. Schulte

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

    Abstract: A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.

    Abstract translation: 多核数据处理器包括多个数据处理器核心和一个电路。 多个数据处理器核心各自包括具有用于接收空闲信号的第一输入的功率状态控制器，用于接收释放信号的第二输入，用于接收控制信号的第三输入和用于提供当前功率状态的输出。 响应于空闲信号，电源状态控制器使相应的数据处理器核进入空闲状态。 响应于释放信号，功率状态控制器根据控制信号将当前功率状态从空闲状态改变到活动状态。 电路耦合到多个数据处理器核心中的每一个，以响应于多个数据处理器核心中的当前功率状态来提供控制信号。

    DIE-STACKED MEMORY DEVICE PROVIDING DATA TRANSLATION
    8.
    发明申请
    DIE-STACKED MEMORY DEVICE PROVIDING DATA TRANSLATION 有权
    提供数据翻译的DIE堆叠存储器件

    公开(公告)号：US20140181458A1

    公开(公告)日：2014-06-26

    申请号：US13726143

    申请日：2012-12-23

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Gabriel H. Loh ,  Bradford M. Beckmann ,  James M. O'Connor ,  Michael Ignatowski ,  Michael J. Schulte ,  Lisa R. Hsu ,  Nuwan S. Jayasena

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.

    Abstract translation: 芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。 由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。 由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。

    Redundant Threading for Improved Reliability
    9.
    发明申请
    Redundant Threading for Improved Reliability 审中-公开
    冗余线程提高可靠性

    公开(公告)号：US20140156975A1

    公开(公告)日：2014-06-05

    申请号：US13690841

    申请日：2012-11-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Vilas SRIDHARAN ,  James M. O'Connor ,  Steven K. Reinhardt ,  Nuwan S. Jayasena ,  Michael J. Schulte ,  Dean A. Liberty

    IPC: G06F9/30

    CPC classification number: G06F9/3861 ,  G06F9/3851 ,  G06F9/3887 ,  G06F11/1641 ,  G06F11/1691 ,  G06F11/1695

    Abstract: In some embodiments, a method for improving reliability in a processor is provided. The method can include replicating input data for first and second lanes of a processor, the first and second lanes being located in a same cluster of the processor and the first and second lanes each generating a respective value associated with an instruction to be executed in the respective lane, and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match.

    Abstract translation: 在一些实施例中，提供了一种用于提高处理器中的可靠性的方法。 该方法可以包括为处理器的第一和第二通道复制输入数据，第一和第二通道位于处理器的相同簇中，并且第一和第二通道各自产生与将要执行的指令相关联的相应值 并且响应于确定所生成的值不匹配，提供所生成的值不匹配的指示。

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