Invention Grant
- Patent Title: Bias circuits and methods for stacked devices
- Patent Title (中): 偏置电路和堆叠器件的方法
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Application No.: US14298665Application Date: 2014-06-06
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Publication No.: US09252713B2Publication Date: 2016-02-02
- Inventor: Joonhoi Hur , Paul Joseph Draxler , Calogero Presti , Marco Cassia
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Fountainhead Law Group P.C.
- Main IPC: H03F3/04
- IPC: H03F3/04 ; H03G3/00 ; H03F1/02 ; H03F3/19 ; H03F3/21 ; H03F1/22 ; H03F3/193

Abstract:
Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node. A modulated power supply voltage and an input signal produce a voltage at the output node. The modulated power supply voltage is provided as an input to the bias circuit. Bias voltages are generated that change with the power supply voltage. In one embodiment, particular transistors in the stack are biased so that their control terminals are effectively short circuited when the power supply voltage is reduced.
Public/Granted literature
- US20150244322A1 BIAS CIRCUITS AND METHODS FOR STACKED DEVICES Public/Granted day:2015-08-27
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