公开(公告)号：US20150244322A1

公开(公告)日：2015-08-27

申请号：US14298665

申请日：2014-06-06

Applicant: QUALCOMM Incorporated

Inventor： Joonhoi Hur ,  Paul Joseph Draxler ,  Calogero Presti ,  Marco Cassia

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/19

CPC classification number: H03F1/0211 ,  H03F1/0222 ,  H03F1/0266 ,  H03F1/223 ,  H03F3/19 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/108 ,  H03F2200/18 ,  H03F2200/451 ,  H03F2200/61

Abstract: Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node. A modulated power supply voltage and an input signal produce a voltage at the output node. The modulated power supply voltage is provided as an input to the bias circuit. Bias voltages are generated that change with the power supply voltage. In one embodiment, particular transistors in the stack are biased so that their control terminals are effectively short circuited when the power supply voltage is reduced.

Abstract translation: 本公开的实施例包括用于向堆叠晶体管产生偏置电压的偏置电路。 在一个实施例中，堆叠晶体管耦合在输入晶体管和输出节点之间。 调制电源电压和输入信号在输出节点产生电压。 调制电源电压被提供给偏置电路的输入。 产生随着电源电压而变化的偏压。 在一个实施例中，堆叠中的特定晶体管被偏置，使得当电源电压降低时，它们的控制端子有效地短路。

公开(公告)号：US09252713B2

公开(公告)日：2016-02-02

申请号：US14298665

申请日：2014-06-06

Applicant: QUALCOMM Incorporated

Inventor： Joonhoi Hur ,  Paul Joseph Draxler ,  Calogero Presti ,  Marco Cassia

IPC: H03F3/04 ,  H03G3/00 ,  H03F1/02 ,  H03F3/19 ,  H03F3/21 ,  H03F1/22 ,  H03F3/193

CPC classification number: H03F1/0211 ,  H03F1/0222 ,  H03F1/0266 ,  H03F1/223 ,  H03F3/19 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/108 ,  H03F2200/18 ,  H03F2200/451 ,  H03F2200/61

Abstract: Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node. A modulated power supply voltage and an input signal produce a voltage at the output node. The modulated power supply voltage is provided as an input to the bias circuit. Bias voltages are generated that change with the power supply voltage. In one embodiment, particular transistors in the stack are biased so that their control terminals are effectively short circuited when the power supply voltage is reduced.

Abstract translation: 本公开的实施例包括用于向堆叠晶体管产生偏置电压的偏置电路。 在一个实施例中，堆叠晶体管耦合在输入晶体管和输出节点之间。 调制电源电压和输入信号在输出节点产生电压。 调制电源电压被提供给偏置电路的输入。 产生随着电源电压而变化的偏压。 在一个实施例中，堆叠中的特定晶体管被偏置，使得当电源电压降低时，它们的控制端子有效地短路。