发明授权
- 专利标题： Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device
- 专利标题（中）： 半导体集成电路器件及半导体集成电路器件的制造方法
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申请号： US14111549申请日： 2012-04-09
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公开(公告)号： US09287259B2公开(公告)日： 2016-03-15
- 发明人: Hirofumi Shinohara , Yukio Nishida , Katsuyuki Horita , Tomohiro Yamashita , Hidekazu Oda
- 申请人： Hirofumi Shinohara , Yukio Nishida , Katsuyuki Horita , Tomohiro Yamashita , Hidekazu Oda
- 申请人地址： JP Tokyo
- 专利权人： Renesas Electronics Corporation
- 当前专利权人： Renesas Electronics Corporation
- 当前专利权人地址： JP Tokyo
- 代理机构： Shapiro, Gabor and Rosenberger, PLLC
- 优先权： JP2011-089693 20110414
- 国际申请： PCT/JP2012/059642 WO 20120409
- 国际公布： WO2012/141122 WO 20121018
- 主分类号： H01L27/088
- IPC分类号： H01L27/088 ; H01L29/66 ; H01L21/8238
摘要：
MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.