公开(公告)号：US20140035055A1

公开(公告)日：2014-02-06

申请号：US14111549

申请日：2012-04-09

申请人： Hirofumi Shinohara ,  Yukio Nishida ,  Katsuyuki Horita ,  Tomohiro Yamashita ,  Hidekazu Oda

发明人： Hirofumi Shinohara ,  Yukio Nishida ,  Katsuyuki Horita ,  Tomohiro Yamashita ,  Hidekazu Oda

IPC分类号： H01L27/088 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/66477

摘要： MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.

摘要翻译： 32nm技术节点之后的MISFET具有高k栅极绝缘膜和金属栅电极。 这样的MISFET的问题是，随后的高温热处理，n-MISFET和p-MISFET的阈值电压的绝对值不可避免地增加。 因此，通过在High-k栅极绝缘膜上形成各种阈值电压调整金属膜并将膜分量从它们引入到高k栅极绝缘膜中来控制阈值电压。 然而，本发明人揭示了引入到n-MISFET的高k栅极绝缘膜中的镧等可能通过随后的热处理转移到STI区域。 根据本发明的半导体集成电路器件在n-MISFET的栅极堆叠的下方和周围的元件隔离区域的表面部分中设置有N沟道阈值电压调节元件向外扩散防止区域。

公开(公告)号：US09287259B2

公开(公告)日：2016-03-15

申请号：US14111549

申请日：2012-04-09

申请人： Hirofumi Shinohara ,  Yukio Nishida ,  Katsuyuki Horita ,  Tomohiro Yamashita ,  Hidekazu Oda

发明人： Hirofumi Shinohara ,  Yukio Nishida ,  Katsuyuki Horita ,  Tomohiro Yamashita ,  Hidekazu Oda

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L27/088 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/66477

摘要： MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.

摘要翻译： 32nm技术节点之后的MISFET具有高k栅极绝缘膜和金属栅电极。 这样的MISFET的问题是，随后的高温热处理，n-MISFET和p-MISFET的阈值电压的绝对值不可避免地增加。 因此，通过在High-k栅极绝缘膜上形成各种阈值电压调节金属膜并将膜分量从它们引入高k栅极绝缘膜来控制阈值电压。 然而，本发明人揭示了引入到n-MISFET的高k栅极绝缘膜中的镧等可能通过随后的热处理转移到STI区域。 根据本发明的半导体集成电路器件在n-MISFET的栅极堆叠的下方和周围的元件隔离区域的表面部分中设置有N沟道阈值电压调节元件向外扩散防止区域。

公开(公告)号：US20070111427A1

公开(公告)日：2007-05-17

申请号：US11599382

申请日：2006-11-15

申请人： Tomohiro Yamashita ,  Yukio Nishida ,  Hidekazu Oda

发明人： Tomohiro Yamashita ,  Yukio Nishida ,  Hidekazu Oda

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7843

摘要： The semiconductor device which can apply the stress application technology to a channel part by a liner film to MISFET including a full silicidation gate electrode, and its manufacturing method are realized. The first liner silicon nitride film is formed on the semiconductor substrate MISFET formed. Insulating films, such as a silicon oxide film, are formed on the first liner silicon nitride film so that it may fully fill up the side of a gate electrode. Next, flattening processing is performed to an insulating film and the first liner silicon nitride film, and a polysilicon gate electrode is exposed. An insulating film is removed leaving the first liner silicon nitride film. The full silicidation of the exposed gate electrode is done, and the second liner silicon nitride film that covers the first liner silicon nitride film and the exposed full silicidation gate electrode is formed.

摘要翻译： 实现了通过衬垫膜将应力施加技术应用于包括全硅化物栅电极的MISFET在内的半导体器件及其制造方法。 第一衬里氮化硅膜形成在形成的半导体衬底MISFET上。 在第一衬垫氮化硅膜上形成诸如氧化硅膜的绝缘膜，使得其可以完全填满栅电极的侧面。 接着，对绝缘膜进行平坦化处理，露出第一衬垫氮化硅膜和多晶硅栅电极。 除去留下第一衬里氮化硅膜的绝缘膜。 完成暴露的栅电极的全硅化，形成覆盖第一衬垫氮化硅膜和暴露的全硅化栅电极的第二衬垫氮化硅膜。

公开(公告)号：US20070007602A1

公开(公告)日：2007-01-11

申请号：US11478669

申请日：2006-07-03

申请人： Hidekazu Oda ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

发明人： Hidekazu Oda ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

IPC分类号： H01L29/94

CPC分类号： H01L21/823842

摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.

摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

公开(公告)号：US06335252B1

公开(公告)日：2002-01-01

申请号：US09564550

申请日：2000-05-04

申请人： Toshiyuki Oishi ,  Yukio Nishida ,  Hirokazu Sayama ,  Hidekazu Oda

发明人： Toshiyuki Oishi ,  Yukio Nishida ,  Hirokazu Sayama ,  Hidekazu Oda

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

摘要： An MIS transistor manufacturing method which can prevent unwanted diffusion of extensions caused by the drive to the source/drain so that the diffusion of the source/drain and the diffusion of the extensions can independently be controlled so as to obtain optimum structure for each. Source/drain are formed by ion implantation using, as a mask, L-shaped silicon nitride films formed on sides of a gate electrode and silicon oxide films covering the silicon nitride films. The silicon oxide films are then removed leaving the silicon nitride films. Impurity ions are then ion-implanted into the main surface of the silicon substrate through the silicon nitride films. Since the silicon nitride films are thicker in the vicinity of the gate electrode and thinner in the vicinity of the source/drain, this process forms extensions penetrating under the gate electrode for a small distance.

摘要翻译： 一种MIS晶体管制造方法，其可以防止由源极/漏极的驱动引起的延伸部的不期望的扩散，从而可以独立地控制源极/漏极的扩散和扩展部的扩散，从而获得每个的最佳结构。 作为掩模，通过离子注入形成源极/漏极，形成在栅电极的侧面上的L形氮化硅膜和覆盖氮化硅膜的氧化硅膜。 然后去除氧化硅膜，留下氮化硅膜。 然后通过氮化硅膜将杂质离子离子注入硅衬底的主表面。 由于氮化硅膜在栅电极附近较厚并且在源极/漏极附近较薄，所以该工艺形成了在栅电极下方一小段距离的延伸。

公开(公告)号：US06600195B1

公开(公告)日：2003-07-29

申请号：US09637870

申请日：2000-08-15

申请人： Yukio Nishida ,  Hirokazu Sayama ,  Hidekazu Oda ,  Toshiyuki Oishi

发明人： Yukio Nishida ,  Hirokazu Sayama ,  Hidekazu Oda ,  Toshiyuki Oishi

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823456 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/7833

摘要： A semiconductor device capable of preventing variations in threshold voltage and having high reliability is provided. The semiconductor device includes a semiconductor substrate having a semiconductor region, and a field-effect transistor. The field-effect transistor includes a gate electrode, source and drain regions, and a channel region. The channel region includes a pair of lightly doped impurity regions having a relatively low impurity concentration as well as a heavily doped impurity region located between the lightly doped impurity regions and having a relatively high impurity concentration.

摘要翻译： 提供能够防止阈值电压变化并具有高可靠性的半导体器件。 半导体器件包括具有半导体区域的半导体衬底和场效应晶体管。 场效应晶体管包括栅电极，源极和漏极区以及沟道区。 沟道区包括杂质浓度相对较低的一对轻掺杂杂质区，以及位于轻掺杂杂质区之间并具有较高杂质浓度的重掺杂杂质区。

公开(公告)号：US06740939B2

公开(公告)日：2004-05-25

申请号：US10100090

申请日：2002-03-19

申请人： Hirokazu Sayama ,  Yukio Nishida ,  Kazunobu Ohta ,  Hidekazu Oda

发明人： Hirokazu Sayama ,  Yukio Nishida ,  Kazunobu Ohta ,  Hidekazu Oda

IPC分类号： H01L2976

CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823842

摘要： CMOS transistors which can satisfy demand for size reduction and demand for reliability and a manufacturing method thereof are provided. A buried-channel type PMOS transistor is provided only in a CMOS transistor (100B) designed for high voltage; surface-channel type NMOS transistors are formed in a low-voltage NMOS region (LNR) and a high-voltage NMOS region (HNR), and a surface-channel type PMOS transistor is formed in a low-voltage PMOS region (LPR).

摘要翻译： 提供了能够满足尺寸减小和可靠性要求的CMOS晶体管及其制造方法。 掩埋沟道型PMOS晶体管仅设置在高电压设计的CMOS晶体管（100B）中; 表面沟道型NMOS晶体管形成在低压NMOS区域（LNR）和高压NMOS区域（HNR）中，并且在低压PMOS区域（LPR）中形成表面沟道型PMOS晶体管。

公开(公告)号：US06506651B2

公开(公告)日：2003-01-14

申请号：US09986581

申请日：2001-11-09

申请人： Hirokazu Sayama ,  Hidekazu Oda ,  Yukio Nishida ,  Toshiyuki Oishi

发明人： Hirokazu Sayama ,  Hidekazu Oda ,  Yukio Nishida ,  Toshiyuki Oishi

IPC分类号： H01L21336

CPC分类号： H01L29/41766 ,  H01L21/26586 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

摘要： There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate (1), an element isolation insulation film (2), a gate structure selectively formed on the main surface of the silicon substrate (1), and a sidewall (6) formed on the side face of the gate structure. The gate structure has a laminated structure with a gate insulation film (3) formed of a silicon oxide film, a gate electrode (4) formed of polysilicon, and a cobalt silicide layer (5) stacked in this order. The semiconductor device further comprises a source/drain region (7) selectively formed in the main surface of the silicon substrate (1) and a cobalt silicide layer (8) formed in the main surface of the silicon substrate (1), extending to a point under an end portion of the gate structure from a portion of the source/drain region (7) exposed from the sidewall 6 and the gate structure.

公开(公告)号：US06734523B2

公开(公告)日：2004-05-11

申请号：US09395184

申请日：1999-09-14

申请人： Shuuichi Ueno ,  Tomohiro Yamashita ,  Hidekazu Oda

发明人： Shuuichi Ueno ,  Tomohiro Yamashita ,  Hidekazu Oda

IPC分类号： H01L2900

CPC分类号： H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  Y10S257/903

摘要： A semiconductor device including a well divided into a plurality of parts by a trench, to effect a reduction in layout area, and a manufacturing method thereof. In the semiconductor device, an element isolation film is formed such as to have to a depth from the main surface of a semiconductor substrate, and the area from the main surface of the substrate to the depth is divided into a plurality of first regions. A first well is formed in each of the first regions. A second well is formed in a second region deeper than the first well in the substrate, and the second well is in contact with some of the first wells.

摘要翻译： 一种半导体器件，其包括通过沟槽被细分为多个部分，以实现布局面积的减小及其制造方法。 在半导体器件中，元件隔离膜形成为具有从半导体衬底的主表面的深度，并且从衬底的主表面到深度的区域被分成多个第一区域。 在每个第一区域中形成第一孔。 第二阱形成在比衬底中的第一阱更深的第二区域中，并且第二阱与一些第一阱接触。

公开(公告)号：US06475844B1

公开(公告)日：2002-11-05

申请号：US09629485

申请日：2000-07-31

申请人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

发明人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L21/28518 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/4983 ,  H01L29/66659

摘要： A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.

摘要翻译： 当扩散区域（7a）连接到位线并且扩散区域（8a）连接到栅极电极（3a）的远离存储节点的表面的一部分中时，形成硅化区域（11a） 存储节点。 在与位线连接的扩散区域（7a）的表面形成硅化区域（12a）。 提供一种MOSFET，其抑制从存储节点到栅电极的漏电流并且降低连接到位线的扩散区域的电阻和所述栅电极的电阻。