摘要:
MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.
摘要:
MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.
摘要:
A semiconductor substrate is covered with a resist mask and then an opening for exposing a whole upper surface of a polysilicon gate is formed by photo lithography and dry etching. Thereafter, nitrogen ions are implanted into the polysilicon gate through the opening. Implantation energy at this time is set so that the implanted ions may not break through the polysilicon gate.
摘要:
P wells (11, 12) having different impurity profiles are adjacently formed in a surface (50S) of a semiconductor substrate (50). A P-type layer (20) having lower resistivity than the P wells (11, 12) is formed in the surface (50S) across the P wells (11, 12), so that the P wells (11, 12) are electrically connected with each other through the P-type layer (20). Contacts (31, 32) fill in contact holes (70H1, 70H2) formed in an interlayer isolation film (70) respectively in contact with the P-type layer (20). The contacts (31, 32) are connected to a wire (40). The wire (70) is connected to a prescribed potential, thereby fixing the P wells (11, 12) to prescribed potentials through the contacts (31, 32) and the P-type layer (20). Thus, the potentials of the wells can be stably fixed and the layout area of elements for fixing the aforementioned potentials can be reduced.
摘要:
Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.
摘要:
The top ends of polysilicon gate electrodes with different gate lengths are formed so as to be equally high and lower than the top end of the side wall. A metal film is formed so as to cover the polysilicon gate electrodes, followed by silicidation by thermal treatment. Since the top ends of the polysilicon gate electrodes are formed lower than the top end of the side wall, a silicon side reaction is not accelerated even in the case of a fine gate length, and proceeds in a one-dimensional manner. As a result, full-silicide gate electrodes having a uniform metal composition ratio can be stably formed even using the polysilicon gates with different gate lengths.
摘要:
In a trench (2), an oxynitride film (31ON1) and a silicon oxide film (31O1) are positioned between a doped silicon oxide film (31D) and a substrate (1), and a silicon oxide film (31O2) is positioned closer to the entrance of the trench (2) than the doped silicon oxide film (31D). The oxynitride film (31ON1) is formed by a nitridation process utilizing the silicon oxide film (31O1). The vicinity of the entrance of the trench (2) is occupied by the silicon oxide films (31O1, 31O2) and the oxynitride film (31ON1).
摘要:
Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.
摘要:
There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0≦x
摘要翻译:提供了一种能够在由沟槽型元件隔离部分包围的有源区域中形成的场效应晶体管中提供期望的操作特性的技术。 元件隔离部分包括沟槽型元件隔离膜,各自包括硅膜或氧化硅膜的扩散防止膜,并且在沟槽型元件隔离膜的顶表面上形成厚度为10至20nm的氧化硅 形成在扩散防止膜的上表面上的厚度为0.5〜2nm的膜。 防扩散膜的组成为SiOx(0 @ x <2)。 沟槽型元件隔离膜和氧化硅膜的组成均为SiO 2。
摘要:
To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer.