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1.发明申请SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权半导体集成电路装置及制造半导体集成电路装置的方法公开(公告)号：US20140035055A1
公开(公告)日：2014-02-06
申请号：US14111549
申请日：2012-04-09
IPC分类号： H01L27/088 , H01L29/66
CPC分类号： H01L27/088 , H01L21/823842 , H01L21/823878 , H01L29/66477
摘要： MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.
摘要翻译： 32nm技术节点之后的MISFET具有高k栅极绝缘膜和金属栅电极。 这样的MISFET的问题是，随后的高温热处理，n-MISFET和p-MISFET的阈值电压的绝对值不可避免地增加。 因此，通过在High-k栅极绝缘膜上形成各种阈值电压调整金属膜并将膜分量从它们引入到高k栅极绝缘膜中来控制阈值电压。 然而，本发明人揭示了引入到n-MISFET的高k栅极绝缘膜中的镧等可能通过随后的热处理转移到STI区域。 根据本发明的半导体集成电路器件在n-MISFET的栅极堆叠的下方和周围的元件隔离区域的表面部分中设置有N沟道阈值电压调节元件向外扩散防止区域。
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2.发明授权Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device 有权半导体集成电路器件及半导体集成电路器件的制造方法公开(公告)号：US09287259B2
公开(公告)日：2016-03-15
申请号：US14111549
申请日：2012-04-09
IPC分类号： H01L27/088 , H01L29/66 , H01L21/8238
CPC分类号： H01L27/088 , H01L21/823842 , H01L21/823878 , H01L29/66477
摘要： MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.
摘要翻译： 32nm技术节点之后的MISFET具有高k栅极绝缘膜和金属栅电极。 这样的MISFET的问题是，随后的高温热处理，n-MISFET和p-MISFET的阈值电压的绝对值不可避免地增加。 因此，通过在High-k栅极绝缘膜上形成各种阈值电压调节金属膜并将膜分量从它们引入高k栅极绝缘膜来控制阈值电压。 然而，本发明人揭示了引入到n-MISFET的高k栅极绝缘膜中的镧等可能通过随后的热处理转移到STI区域。 根据本发明的半导体集成电路器件在n-MISFET的栅极堆叠的下方和周围的元件隔离区域的表面部分中设置有N沟道阈值电压调节元件向外扩散防止区域。
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公开(公告)号：US20080113480A1
公开(公告)日：2008-05-15
申请号：US11939941
申请日：2007-11-14
IPC分类号： H01L21/8236
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L21/32155 , H01L21/823835 , H01L21/823842 , H01L21/82385 , H01L21/823857
摘要： A semiconductor substrate is covered with a resist mask and then an opening for exposing a whole upper surface of a polysilicon gate is formed by photo lithography and dry etching. Thereafter, nitrogen ions are implanted into the polysilicon gate through the opening. Implantation energy at this time is set so that the implanted ions may not break through the polysilicon gate.
摘要翻译： 用抗蚀剂掩模覆盖半导体衬底，然后通过光刻和干蚀刻形成用于暴露多晶硅栅极的整个上表面的开口。 此后，通过开口将氮离子注入到多晶硅栅极中。 此时的植入能量被设定为使得注入的离子不会穿过多晶硅栅极。
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4.发明申请SEMICONDUCTOR DEVICE WHICH HAS MOS STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开具有MOS结构的半导体器件及其制造方法公开(公告)号：US20080308869A1
公开(公告)日：2008-12-18
申请号：US12194631
申请日：2008-08-20
申请人： Hidekazu ODA , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
发明人： Hidekazu ODA , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
IPC分类号： H01L29/00
CPC分类号： H01L21/823842
摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered.The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.
摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。
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公开(公告)号：US20070111427A1
公开(公告)日：2007-05-17
申请号：US11599382
申请日：2006-11-15
申请人： Tomohiro Yamashita , Yukio Nishida , Hidekazu Oda
发明人： Tomohiro Yamashita , Yukio Nishida , Hidekazu Oda
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/823835 , H01L21/823864 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/7842 , H01L29/7843
摘要： The semiconductor device which can apply the stress application technology to a channel part by a liner film to MISFET including a full silicidation gate electrode, and its manufacturing method are realized. The first liner silicon nitride film is formed on the semiconductor substrate MISFET formed. Insulating films, such as a silicon oxide film, are formed on the first liner silicon nitride film so that it may fully fill up the side of a gate electrode. Next, flattening processing is performed to an insulating film and the first liner silicon nitride film, and a polysilicon gate electrode is exposed. An insulating film is removed leaving the first liner silicon nitride film. The full silicidation of the exposed gate electrode is done, and the second liner silicon nitride film that covers the first liner silicon nitride film and the exposed full silicidation gate electrode is formed.
摘要翻译： 实现了通过衬垫膜将应力施加技术应用于包括全硅化物栅电极的MISFET在内的半导体器件及其制造方法。 第一衬里氮化硅膜形成在形成的半导体衬底MISFET上。 在第一衬垫氮化硅膜上形成诸如氧化硅膜的绝缘膜，使得其可以完全填满栅电极的侧面。 接着，对绝缘膜进行平坦化处理，露出第一衬垫氮化硅膜和多晶硅栅电极。 除去留下第一衬里氮化硅膜的绝缘膜。 完成暴露的栅电极的全硅化，形成覆盖第一衬垫氮化硅膜和暴露的全硅化栅电极的第二衬垫氮化硅膜。
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6.发明申请Semiconductor device which has MOS structure and method of manufacturing the same 审中-公开具有MOS结构的半导体器件及其制造方法公开(公告)号：US20070007602A1
公开(公告)日：2007-01-11
申请号：US11478669
申请日：2006-07-03
申请人： Hidekazu Oda , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
发明人： Hidekazu Oda , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
IPC分类号： H01L29/94
CPC分类号： H01L21/823842
摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.
摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。
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公开(公告)号：US06777758B2
公开(公告)日：2004-08-17
申请号：US09754325
申请日：2001-01-05
IPC分类号： H01L2976
CPC分类号： H01L21/28512 , H01L21/76895 , H01L21/823493
摘要： P wells (11, 12) having different impurity profiles are adjacently formed in a surface (50S) of a semiconductor substrate (50). A P-type layer (20) having lower resistivity than the P wells (11, 12) is formed in the surface (50S) across the P wells (11, 12), so that the P wells (11, 12) are electrically connected with each other through the P-type layer (20). Contacts (31, 32) fill in contact holes (70H1, 70H2) formed in an interlayer isolation film (70) respectively in contact with the P-type layer (20). The contacts (31, 32) are connected to a wire (40). The wire (70) is connected to a prescribed potential, thereby fixing the P wells (11, 12) to prescribed potentials through the contacts (31, 32) and the P-type layer (20). Thus, the potentials of the wells can be stably fixed and the layout area of elements for fixing the aforementioned potentials can be reduced.
摘要翻译： 具有不同杂质分布的P阱（11,12）相邻地形成在半导体衬底（50）的表面（50S）中。 在P阱（11,12）的表面（50S）中形成具有比P阱（11,12）低的电阻率的P型层（20），使得P阱（11,12）电 通过P型层（20）彼此连接。 接触件（31,32）分别填充形成在与P型层（20）接触的层间隔离膜（70）中的接触孔（70H1,70H2）。 触头（31,32）连接到导线（40）上。 电线（70）连接到规定电位，由此通过触点（31,32）和P型层（20）将P阱（11,12）固定到规定的电位。 因此，可以稳定地固定阱的电位，并且可以减少用于固定上述电位的元件的布局面积。
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公开(公告)号：US08592284B2
公开(公告)日：2013-11-26
申请号：US12495070
申请日：2009-06-30
IPC分类号： H01L21/76
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/7846
摘要： Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.
摘要翻译： 提供一种半导体器件，其可以形成具有接近设计尺寸的尺寸的元件区域，抑制类似于栅极引起的漏极泄漏的现象，并且进一步抑制通过导电的氧化对元件区域施加的压缩应力 电影; 以及半导体装置的制造方法。 沟槽在半导体基板的主表面上制成。 通过氧化每个沟槽的壁表面，在壁表面上形成第一氧化膜。 嵌入的导电膜被形成为嵌入到沟槽中。 嵌入的导电膜在含有活性氧化物质的气氛中被氧化，从而形成第二氧化物膜。 通过CVD或涂布法在第二氧化物膜上形成第三氧化物膜。
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公开(公告)号：US20100044802A1
公开(公告)日：2010-02-25
申请号：US12495070
申请日：2009-06-30
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/7846
摘要： Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.
摘要翻译： 提供一种半导体器件，其可以形成具有接近设计尺寸的尺寸的元件区域，抑制类似于栅极引起的漏极泄漏的现象，并且进一步抑制通过导电的氧化对元件区域施加的压缩应力 电影; 以及半导体装置的制造方法。 沟槽在半导体基板的主表面上制成。 通过氧化每个沟槽的壁表面，在壁表面上形成第一氧化膜。 嵌入的导电膜被形成为嵌入到沟槽中。 嵌入的导电膜在含有活性氧化物质的气氛中被氧化，从而形成第二氧化膜。 通过CVD或涂布法在第二氧化物膜上形成第三氧化物膜。
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公开(公告)号：US20070138574A1
公开(公告)日：2007-06-21
申请号：US11563500
申请日：2006-11-27
IPC分类号： H01L29/76
CPC分类号： H01L21/823443 , H01L21/28114 , H01L21/823456 , H01L21/823468 , H01L21/823835 , H01L21/82385 , H01L21/823864 , H01L29/42376 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： The top ends of polysilicon gate electrodes with different gate lengths are formed so as to be equally high and lower than the top end of the side wall. A metal film is formed so as to cover the polysilicon gate electrodes, followed by silicidation by thermal treatment. Since the top ends of the polysilicon gate electrodes are formed lower than the top end of the side wall, a silicon side reaction is not accelerated even in the case of a fine gate length, and proceeds in a one-dimensional manner. As a result, full-silicide gate electrodes having a uniform metal composition ratio can be stably formed even using the polysilicon gates with different gate lengths.
摘要翻译： 具有不同栅极长度的多晶硅栅电极的顶端形成为等于高于侧壁的顶端的高度。 形成金属膜以覆盖多晶硅栅电极，然后通过热处理进行硅化。 由于多晶硅栅电极的顶端形成为低于侧壁的顶端，因此即使在精细栅极长度的情况下，硅侧反应也不会加速，并且以一维方式进行。 结果，即使使用具有不同栅极长度的多晶硅栅极，也可以稳定地形成具有均匀金属组成比的全硅化物栅电极。
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