Briefly, in accordance with one or more embodiments, an apparatus to test a semiconductor device comprises a controller configured to perform one or more tests on the semiconductor device, a reduce low pin count (RLPC) circuit configured to write data to the semiconductor device or read data from the semiconductor device at a double data rate (DDR) with respect to a single data rate (SDR), and pad logic to couple to the semiconductor device, the pad logic configured to provide a trimmable data access time from clock (tAC) signal to select different access times of a single data rate (SDR) or a double data rate (DDR) mode of operation, wherein a loading time or an unloading time of the semiconductor device being tested, or a combination thereof, is reduced when a DDR mode is selected.