公开(公告)号：US09293224B1

公开(公告)日：2016-03-22

申请号：US14569983

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Dzung Nguyen ,  Luyen T. Vu

IPC: G11C7/00 ,  G11C29/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/02 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/10

CPC classification number: G11C29/08 ,  G01R31/3177 ,  G01R31/318536 ,  G11C7/1093 ,  G11C11/401 ,  G11C16/32 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50012

Abstract: Briefly, in accordance with one or more embodiments, an apparatus to test a semiconductor device comprises a controller configured to perform one or more tests on the semiconductor device, a reduce low pin count (RLPC) circuit configured to write data to the semiconductor device or read data from the semiconductor device at a double data rate (DDR) with respect to a single data rate (SDR), and pad logic to couple to the semiconductor device, the pad logic configured to provide a trimmable data access time from clock (tAC) signal to select different access times of a single data rate (SDR) or a double data rate (DDR) mode of operation, wherein a loading time or an unloading time of the semiconductor device being tested, or a combination thereof, is reduced when a DDR mode is selected.

Abstract translation: 简而言之，根据一个或多个实施例，一种用于测试半导体器件的装置包括被配置为对半导体器件执行一个或多个测试的控制器，被配置为向半导体器件写入数据的减少的低引脚数（RLPC）电路， 以相对于单个数据速率（SDR）的双倍数据速率（DDR）从所述半导体器件读取数据，以及焊盘逻辑以耦合到所述半导体器件，所述焊盘逻辑被配置为从时钟（tAC）提供可调整的数据访问时间 ）信号以选择单个数据速率（SDR）或双数据速率（DDR）操作模式的不同访问时间，其中正被测试的半导体器件的加载时间或卸载时间或其组合被减少，当 选择DDR模式。

公开(公告)号：US09620229B2

公开(公告)日：2017-04-11

申请号：US14926401

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Mark Helm ,  Jung Sheng Hoei ,  Aaron Yip ,  Dzung Nguyen

IPC: G11C16/04 ,  G11C16/26 ,  G11C7/18 ,  G11C8/14 ,  H01L27/02 ,  H01L27/06 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/12 ,  G11C7/12 ,  G11C13/00 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C5/12 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0023 ,  G11C16/24 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  Y10T29/49155

Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.