Invention Grant
- Patent Title: Methods and structures for back end of line integration
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Application No.: US14805443Application Date: 2015-07-21
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Publication No.: US09293363B2Publication Date: 2016-03-22
- Inventor: Sunil K. Singh , Ravi P. Srivastava , Mark A. Zaleski , Akshey Sehgal
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams Morgan, P.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/4763 ; H01L21/311 ; H01L21/768 ; H01L23/532 ; H01L23/528 ; H01L23/522 ; H01L21/02 ; H01L21/3105 ; H01L21/3213
Abstract:
Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
Public/Granted literature
- US20150332959A1 METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION Public/Granted day:2015-11-19
Information query
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