公开(公告)号：US20200013678A1

公开(公告)日：2020-01-09

申请号：US16026130

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Akshey Sehgal ,  Xinyuan Dou ,  Sunil K. Singh ,  Ravi P. Srivastava ,  Haiting Wang ,  Scott H. Beasor

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L23/48 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

公开(公告)号：US20200013551A1

公开(公告)日：2020-01-09

申请号：US16550431

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Jagar Singh

IPC: H01F41/063 ,  H01F41/12 ,  H01F5/00 ,  H01F5/06 ,  H01F41/34 ,  H01F17/00 ,  H01F41/04 ,  H01L49/02 ,  H01L21/00

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

公开(公告)号：US20190206718A1

公开(公告)日：2019-07-04

申请号：US15860121

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Shao Beng Law ,  Sunil K. Singh ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02118 ,  H01L21/02274 ,  H01L21/31058 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76828 ,  H01L23/528 ,  H01L23/53295 ,  H01L2221/1047

Abstract: Interconnect structures and methods for forming an interconnect structure. First and second metallization structures are formed in an intralayer dielectric layer. The intralayer dielectric layer is removed to form a cavity with an entrance between the first and second metallization structures. A dielectric layer is deposited on surfaces surrounding the cavity, over the first metallization structure, and over the second metallization structure. A sacrificial material is formed inside the cavity after the dielectric layer is deposited. A cap layer is deposited on the dielectric layer over the first metallization structure, the dielectric layer over the second metallization structure, and the sacrificial material inside the cavity to close the entrance to the cavity. After the cap layer is deposited, the sacrificial material is removed from the cavity. The dielectric layer and cap layer cooperate to encapsulate an air gap inside the cavity.

公开(公告)号：US20180025936A1

公开(公告)日：2018-01-25

申请号：US15214585

申请日：2016-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Sohan S. Mehta ,  Sherjang Singh ,  Ravi P. Srivastava

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L21/76802 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening and second openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resist material that is removable selective to the hardmask layer.

公开(公告)号：US09293363B2

公开(公告)日：2016-03-22

申请号：US14805443

申请日：2015-07-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L29/66 ,  H01L21/4763 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

公开(公告)号：US20150332959A1

公开(公告)日：2015-11-19

申请号：US14805443

申请日：2015-07-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L21/768

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

Abstract translation: 本发明的实施例提供了一种用于BEOL（后端）集成的半导体结构。 定向自组装（DSA）材料被沉积并退火以形成两个不同的相位区域。 选择性地去除一个相区，并且剩余的相区用作在金属和/或电介质的下层中形成空腔的掩模。 然后重复该过程以形成具有由电介质区域分离的金属图案的复杂结构。

公开(公告)号：US09117822B1

公开(公告)日：2015-08-25

申请号：US14264163

申请日：2014-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L29/66 ,  H01L21/4763 ,  H01L21/31 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

Abstract translation: 本发明的实施例提供了一种用于BEOL（后端）集成的半导体结构。 定向自组装（DSA）材料被沉积并退火以形成两个不同的相位区域。 选择性地去除一个相区，并且剩余的相区用作在金属和/或电介质的下层中形成空腔的掩模。 然后重复该过程以形成具有由电介质区域分离的金属图案的复杂结构。

公开(公告)号：US10777413B2

公开(公告)日：2020-09-15

申请号：US16033714

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuping Ren ,  Guoxiang Ning ,  Haigou Huang ,  Sunil K. Singh

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.

公开(公告)号：US10714380B2

公开(公告)日：2020-07-14

申请号：US16171477

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravi P. Srivastava ,  Sipeng Gu ,  Sunil K. Singh ,  Xinyuan Dou ,  Akshey Sehgal ,  Zhiguo Sun

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

公开(公告)号：US10453605B2

公开(公告)日：2019-10-22

申请号：US15729992

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Jagar Singh

IPC: H01F5/00 ,  H01F41/063 ,  H01F41/12 ,  H01F5/06 ,  H01F41/34 ,  H01F17/00 ,  H01F41/04 ,  H01L21/00 ,  H01L49/02

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.