Invention Grant
US09294112B1 Methods and systems for reducing order-dependent mismatch errors in time-interleaved analog-to-digital converters
有权
用于减少时间交替模数转换器中与阶数有关的失配误差的方法和系统
- Patent Title: Methods and systems for reducing order-dependent mismatch errors in time-interleaved analog-to-digital converters
- Patent Title (中): 用于减少时间交替模数转换器中与阶数有关的失配误差的方法和系统
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Application No.: US14540515Application Date: 2014-11-13
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Publication No.: US09294112B1Publication Date: 2016-03-22
- Inventor: Siddharth Devarajan , Lawrence A. Singer , Prawal Man Shrestha , Pingli Huang
- Applicant: ANALOG DEVICES, INC.
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Patent Capital Group
- Main IPC: H03M1/12
- IPC: H03M1/12 ; H03M1/06 ; H03M1/08 ; H03M1/00

Abstract:
A time-interleaved analog-to-digital converter (ADC) uses M sub-analog-to-digital converters (sub-ADCs) to, according to a sequence, sample an analog input signal to produce digital outputs. When the M sub-ADCs are interleaved, the digital outputs exhibit mismatch errors between the M sub-ADCs due to mismatches between the sub-ADCs. A more second order subtle effect is that the mismatch error for a particular digital output from a particular ADC, due to internal coupling or other such interaction and effects between the M sub-ADCs, can vary depending on which sub-ADC(s) were used before and/or after the particular sub-ADC. If M sub-ADCs are time-interleaved randomly, the mismatches between the M sub-ADCs become a function of the sub-ADC selection pattern in the sequence. The present disclosure describes mechanisms for measuring and reducing these order-dependent mismatches to achieve high dynamic range performance in the time-interleaved ADC.
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