公开(公告)号：US10250250B2

公开(公告)日：2019-04-02

申请号：US15689491

申请日：2017-08-29

Applicant: Analog Devices, Inc.

Inventor： Siddharth Devarajan ,  Lawrence A. Singer

IPC: H03K17/06 ,  H03K17/0412 ,  H03M1/18 ,  H03K17/042 ,  H03K17/00 ,  H03K19/0185 ,  H03K19/017 ,  H03M1/06 ,  H03M1/12

Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.

公开(公告)号：US20140266358A1

公开(公告)日：2014-09-18

申请号：US14187440

申请日：2014-02-24

Applicant: ANALOG DEVICES, INC.

Inventor： Siddharth Devarajan ,  Lawrence A. Singer

IPC: H03K5/01

CPC classification number: H03K5/01 ,  H03H19/006 ,  H03H19/008 ,  H03K2217/0018

Abstract: In one example embodiment, a programmable capacitor array is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry to switch on and off an array of MOSFET switches. The control circuitry turns on a MOSFET to load a capacitance on Vin and turns off the MOSFET to remove the capacitance from Vin in response to a Din control signal. When the intention is to load Vin with the capacitance, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance from Vin, the MOSFET is primarily turned off, however, the MOSFET is still periodically turned on with appropriate voltage levels in response to a clock signal for periods of time when the loading of the capacitance on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system.

Abstract translation: 在一个示例性实施例中，提供可编程电容器阵列用于通过利用控制电路来接通和关闭MOSFET开关阵列来实现低失真并最小化输入（Vin）的线性劣化。 控制电路打开MOSFET以在Vin上加载电容，并关闭MOSFET以响应于Din控制信号从Vin去除电容。 当意图将Vin加载到电容时，MOSFET保持连续。 当意图从Vin去除或卸载电容时，MOSFET主要被关闭，然而，当电容负载上升时，MOSFET的周期性响应于时钟信号，MOSFET仍然周期性地接通适当的电压电平 Vin对系统是可以容忍的，从而确保由于可编程电容阵列系统引起的Vin的最小线性降低。

公开(公告)号：US09793910B1

公开(公告)日：2017-10-17

申请号：US15262325

申请日：2016-09-12

Applicant: ANALOG DEVICES, INC.

Inventor： Siddharth Devarajan

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/1215 ,  H03M1/0634 ,  H03M1/0673 ,  H03M1/1009 ,  H03M1/124

Abstract: A time-interleaved analog-to-digital converter (ADC) uses M analog-to-digital converters to sample an analog input signal to produce digital outputs. The M ADCs, operating in a time-interleaved fashion, can increase the sampling speed several times compared to the sampling speed of just one ADC. The time-interleaved ADC can be programmed and reconfigured to trade one performance metric for another. For example, more time can be given to comparator to improve bit error rate or more time can be given to an amplifier for improved settling which improves SNR, SFDR etc. If the time-interleaved converters are randomized, then the amount of ‘color’ in the noise floor shape can also be traded for other performance metrics.

公开(公告)号：US09106210B2

公开(公告)日：2015-08-11

申请号：US14187440

申请日：2014-02-24

Applicant: ANALOG DEVICES, INC.

Inventor： Siddharth Devarajan ,  Lawrence A. Singer

IPC: H03K5/01 ,  H03H19/00

CPC classification number: H03K5/01 ,  H03H19/006 ,  H03H19/008 ,  H03K2217/0018

Abstract: In one example embodiment, a programmable capacitor array is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry to switch on and off an array of MOSFET switches. The control circuitry turns on a MOSFET to load a capacitance on Vin and turns off the MOSFET to remove the capacitance from Vin in response to a Din control signal. When the intention is to load Vin with the capacitance, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance from Vin, the MOSFET is primarily turned off, however, the MOSFET is still periodically turned on with appropriate voltage levels in response to a clock signal for periods of time when the loading of the capacitance on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system.

Abstract translation: 在一个示例性实施例中，提供可编程电容器阵列用于通过利用控制电路来接通和关闭MOSFET开关阵列来实现低失真并最小化输入（Vin）的线性劣化。 控制电路打开MOSFET以在Vin上加载电容，并关闭MOSFET以响应于Din控制信号从Vin去除电容。 当意图将Vin加载到电容时，MOSFET保持连续。 当意图从Vin去除或卸载电容时，MOSFET主要被关闭，然而，当电容负载上升时，MOSFET的周期性响应于时钟信号，MOSFET仍然周期性地接通适当的电压电平 Vin可以容忍系统，从而确保由于可编程电容阵列系统导致Vin的最小线性退化。

公开(公告)号：US09641166B2

公开(公告)日：2017-05-02

申请号：US14206006

申请日：2014-03-12

Applicant: ANALOG DEVICES, INC.

Inventor： Siddharth Devarajan ,  Lawrence A. Singer

IPC: H03K17/04 ,  H03K17/16 ,  G11C27/02 ,  H03K17/0412

CPC classification number: H03K17/04 ,  G11C27/02 ,  H03K17/04123 ,  H03K2217/0054

Abstract: An apparatus and method for implementing a bootstrapped switching circuit having improved (i.e. faster) turn-on time is provided. In an embodiment, an inner switching loop is implemented in a bootstrapped switching circuit where the inner switching loop is configured to turn on an input switch in the bootstrapped drive circuit independent of the drive circuit output. The embodiment decouples the inner switching loop circuitry from the output drive circuit of the bootstrapped switching circuit, which typically has a larger load capacitance than the inner switching loop. This allows the inner switching loop to turn on the input switch in the bootstrapped switching circuit faster and decreases the turn-on time of the bootstrapped switching circuit.

公开(公告)号：US09525428B2

公开(公告)日：2016-12-20

申请号：US14955905

申请日：2015-12-01

Applicant: ANALOG DEVICES, INC.

Inventor： Siddharth Devarajan ,  Eric Otte ,  Nevena Rakuljic ,  Carroll C. Speir

IPC: H03M1/12 ,  H03M1/10 ,  H03M1/46 ,  H03M3/00

CPC classification number: H03M1/128 ,  H03M1/1019 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468 ,  H03M3/382 ,  H03M3/498

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract translation: 模数转换器（ADC）可能会产生可能影响其性能的错误。 为了提高性能，已经使用许多技术来补偿或纠正错误。 当ADC采用亚微米技术实现时，ADC可以轻松轻松配备一个片上微处理器，用于执行各种数字功能。 片上微处理器和任何合适的数字电路可以实现减少这些错误的功能，从而能够减少某些不必要的伪像，并为高度可配置的ADC提供灵活的平台。 片上微处理器对于随机时间交织ADC特别有用。 此外，随机采样ADC可以并行添加到主ADC用于校准目的。 此外，整个系统可以包括用于校正ADC中的错误的有效实现。

公开(公告)号：US09294112B1

公开(公告)日：2016-03-22

申请号：US14540515

申请日：2014-11-13

Applicant: ANALOG DEVICES, INC.

Inventor： Siddharth Devarajan ,  Lawrence A. Singer ,  Prawal Man Shrestha ,  Pingli Huang

IPC: H03M1/12 ,  H03M1/06 ,  H03M1/08 ,  H03M1/00

CPC classification number: H03M1/121 ,  H03M1/00 ,  H03M1/0604 ,  H03M1/0607 ,  H03M1/0609 ,  H03M1/0612 ,  H03M1/066 ,  H03M1/0836 ,  H03M1/1033 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/124

Abstract: A time-interleaved analog-to-digital converter (ADC) uses M sub-analog-to-digital converters (sub-ADCs) to, according to a sequence, sample an analog input signal to produce digital outputs. When the M sub-ADCs are interleaved, the digital outputs exhibit mismatch errors between the M sub-ADCs due to mismatches between the sub-ADCs. A more second order subtle effect is that the mismatch error for a particular digital output from a particular ADC, due to internal coupling or other such interaction and effects between the M sub-ADCs, can vary depending on which sub-ADC(s) were used before and/or after the particular sub-ADC. If M sub-ADCs are time-interleaved randomly, the mismatches between the M sub-ADCs become a function of the sub-ADC selection pattern in the sequence. The present disclosure describes mechanisms for measuring and reducing these order-dependent mismatches to achieve high dynamic range performance in the time-interleaved ADC.

Abstract translation: 时间交织的模数转换器（ADC）使用M个子模数转换器（sub-ADC），根据一个序列对模拟输入信号进行采样以产生数字输出。 当M个子ADC被交错时，由于子ADC之间的不匹配，数字输出在M个子ADC之间表现出失配误差。 更多的二阶微妙效应是，由于内部耦合或其他此类相互作用和M子ADC之间的影响，来自特定ADC的特定数字输出的失配误差可以根据哪些子ADC 在特定子ADC之前和之后使用。 如果M个子ADC随机进行时间交织，那么M个子ADC之间的失配成为序列中子ADC选择模式的函数。 本公开描述了用于测量和减少这些依赖于顺序的失配以在时间交织的ADC中实现高动态范围性能的机制。

公开(公告)号：US08866652B2

公开(公告)日：2014-10-21

申请号：US13975291

申请日：2013-08-24

Applicant: Analog Devices, Inc.

Inventor： Lawrence A. Singer ,  Siddharth Devarajan

IPC: H03M1/12 ,  G11C27/02 ,  H03K17/04 ,  H03K17/041 ,  H03M1/08

CPC classification number: H03M1/1245 ,  G11C27/02 ,  G11C27/024 ,  H03K17/041 ,  H03M1/0836 ,  H03M1/1215

Abstract: An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels.

Abstract translation: 用于在具有多个通道的交错采样电路中采样的示例性装置，系统和方法。 在一个实施例中，输入时钟用于使采样时钟的转变从第一电压电平相对于第二电压电平彼此相同步。 采样时钟输入到采样电路。 输入时钟切换公共开关，其通过公共路径将每个采样时钟从第一时钟状态转换到第二时钟状态。 从每个采样时钟的第一电压电平到第二电压电平的转换触发在一个通道上采集的采样。 可以升高第一电压电平以驱动采样电路中的开关。 通过公共开关和公共路径同步输出的转换减少了控制通道的采样时钟之间的时序不匹配。

公开(公告)号：US20140253353A1

公开(公告)日：2014-09-11

申请号：US13975291

申请日：2013-08-24

Applicant: ANALOG DEVICES, INC.

Inventor： Lawrence A. Singer ,  Siddharth Devarajan

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  G11C27/02 ,  G11C27/024 ,  H03K17/041 ,  H03M1/0836 ,  H03M1/1215

Abstract: An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels.

Abstract translation: 用于在具有多个通道的交错采样电路中采样的示例性装置，系统和方法。 在一个实施例中，输入时钟用于使采样时钟的转变从第一电压电平相对于第二电压电平彼此相同步。 采样时钟输入到采样电路。 输入时钟切换公共开关，其通过公共路径将每个采样时钟从第一时钟状态转换到第二时钟状态。 从每个采样时钟的第一电压电平到第二电压电平的转换触发在一个通道上采集的采样。 可以升高第一电压电平以驱动采样电路中的开关。 通过公共开关和公共路径同步输出的转换减少了控制通道的采样时钟之间的时序不匹配。