Invention Grant
- Patent Title: Baud rate phase detector with no error latches
- Patent Title (中): 波特率相位检测器,无错误锁存
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Application No.: US14222157Application Date: 2014-03-21
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Publication No.: US09304535B2Publication Date: 2016-04-05
- Inventor: Volodymyr Shvydun , Adam B. Healey , Chaitanya Palusa , Hiep T. Pham
- Applicant: LSI Corporation
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: G06F1/12
- IPC: G06F1/12 ; G06F7/00 ; H04L7/033 ; H04L27/26 ; H03L7/091 ; H04L27/227 ; H04L27/00 ; H04L27/06 ; H04L25/02 ; H03L7/087

Abstract:
Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.
Public/Granted literature
- US20150234423A1 Baud Rate Phase Detector with No Error Latches Public/Granted day:2015-08-20
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