公开(公告)号：US09304535B2

公开(公告)日：2016-04-05

申请号：US14222157

申请日：2014-03-21

Applicant: LSI Corporation

Inventor： Volodymyr Shvydun ,  Adam B. Healey ,  Chaitanya Palusa ,  Hiep T. Pham

IPC: G06F1/12 ,  G06F7/00 ,  H04L7/033 ,  H04L27/26 ,  H03L7/091 ,  H04L27/227 ,  H04L27/00 ,  H04L27/06 ,  H04L25/02 ,  H03L7/087

CPC classification number: G06F1/12 ,  H03L7/087 ,  H03L7/091 ,  H04L7/0338 ,  H04L25/022 ,  H04L27/066 ,  H04L27/2275 ,  H04L27/2695 ,  H04L2027/0067

Abstract: Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.

Abstract translation: 公开了不需要错误锁存器或接收的输入数据的过采样的相位检测器和定时恢复技术。 相位检测方法包括将输入信号分离成N个连续数据位; 比较N个连续数据比特中的至少两个连续数据比特; 估计每个N个连续数据比特的数据比特值; 以及基于由N个连续数据位的数据位值形成的数据位模式和在N个连续数据位中的至少两个连续数据位的比较来确定相位差。

公开(公告)号：US09077574B1

公开(公告)日：2015-07-07

申请号：US14227120

申请日：2014-03-27

Applicant: LSI Corporation

Inventor： Adam B. Healey ,  Chaitanya Palusa ,  Tomasz Prokop ,  Volodymyr Shvydun

IPC: H04L25/03

CPC classification number: H04L25/03057

Abstract: A SerDes receiver device can receive binary signals via wireline channel such that information recovery is primarily or entirely performed via DSP algorithms in the digital domain includes an analog to digital converter, adaptation and calibration blocks, and a sequential n-way parallel equalization data path. The data path provides preliminary equalization of digital input symbols through a feed forward equalizer block followed by a decision feedback equalizer block, to which a k-slice decision feed forward equalizer block is appended for generating equalized hard decision outputs. The decision feed forward equalizer block may include a concatenation of cascading DFFE slices to improve the performance of the data path.

Abstract translation: SerDes接收机设备可以经由有线通道接收二进制信号，使得信息恢复主要或完全通过数字域中的DSP算法执行，包括模数转换器，适配和校准块以及顺序n路并行均衡数据路径。 数据路径通过前馈均衡器块提供数字输入符号的初步均衡，随后是判决反馈均衡器块，附加k片判决前馈均衡器块以产生均衡的硬判决输出。 决定前馈均衡器块可以包括级联DFFE片段的级联以提高数据路径的性能。

公开(公告)号：US08976854B1

公开(公告)日：2015-03-10

申请号：US14193170

申请日：2014-02-28

Applicant: LSI Corporation

Inventor： Adam B. Healey ,  Tomasz Prokop ,  Volodymyr Shvydun ,  Chaitanya Palusa

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03038

Abstract: A reconfigurable P-way parallel N-tap feed forward equalizer includes an adaptive filter configured to generate a series of coefficients (taps) and an input register for storing input symbols. A variable cursor position defined by a parameter corresponding to a position in the input register selects a set of pre-cursor and post-cursor taps for dynamic ISI correction of a like set of pre-cursor and post-cursor symbols. Multiplier banks generate partial result symbols by applying the taps to the set of input symbols, and a set of combiners or adder banks generate equalized output symbols from the partial result symbols. Two multiplexers adjust input symbols and coefficients according to the parameter, and a controller allows selection of an optimal parameter, and thus an optimal variable cursor position. The coefficient corresponding to the parameter may additionally be preset to save storage space.

Abstract translation: 可重新配置的P路并行N抽头前馈均衡器包括被配置为生成一系列系数（抽头）的自适应滤波器和用于存储输入符号的输入寄存器。 由对应于输入寄存器中的位置的参数定义的可变光标位置为一组相似的前置光标和后光标符号选择一组用于动态ISI校正的前置光标和后置光标。 乘法器组通过将抽头应用到输入符号集合来产生部分结果符号，并且一组组合器或加法器组从部分结果符号生成均衡的输出符号。 两个多路复用器根据参数调整输入符号和系数，并且控制器允许选择最佳参数，并因此选择最佳可变光标位置。 可以另外预设与参数对应的系数以节省存储空间。

公开(公告)号：US08837570B2

公开(公告)日：2014-09-16

申请号：US13685993

申请日：2012-11-27

Applicant: LSI Corporation

Inventor： Volodymyr Shvydun ,  Tomasz Prokop

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03057

Abstract: Described embodiments apply equalization to an input signal to a receiver such as a serial-deserializer. The receiver has an analog-to-digital converter (ADC), an M-way parallelizer, N serial buffers, N prefix buffers, and N decision feedback equalizers (DFEs), where M and N are greater than one. The ADC digitizes the input signal to form digitized symbols. The parallelizer assembles the digitized symbols into parallel sets of M digitized symbols. Each serial buffer has slots of M locations per slot and stores one set of M digitized symbols in one of the slots. The DFEs are responsive to common tap weight coefficients and produce parallel sets of M recovered data bits. Each DFE is first trained using sets of past digitized symbols loaded into a corresponding one of the prefix buffers and then processes digitized symbols stored in a corresponding one of the serial buffers.

Abstract translation: 所描述的实施例将均衡化到诸如串行解串器之类的接收器的输入信号。 接收机具有模数转换器（ADC），M路并行器，N个串行缓冲器，N个前缀缓冲器和N个判决反馈均衡器（DFE），其中M和N大于1。 ADC将输入信号数字化，形成数字化符号。 并行化器将数字化符号组装成M个数字化符号的并行集合。 每个串行缓冲器具有每个时隙的M个位置的时隙，并且在一个时隙中存储一组M个数字化符号。 DFE响应于公共抽头权重系数并产生M个恢复数据位的并行集合。 首先使用加载到相应的前缀缓冲器中的过去数字化符号的集合训练每个DFE，然后处理存储在对应的一个串行缓冲器中的数字化符号。

公开(公告)号：US20150256363A1

公开(公告)日：2015-09-10

申请号：US14226915

申请日：2014-03-27

Applicant: LSI Corporation

Inventor： Volodymyr Shvydun ,  Adam B. Healey ,  Chaitanya Palusa

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/03057 ,  H04L25/4917 ,  H04L2025/03535

Abstract: An N-way parallel, unrolled decision feedback equalizer for a SerDes receiver can convert between four-tap PAM-2 and two-tap PAM-4 mode, maximizing hardware through the use of mode control multiplexers. Each of N interleaved parallel branches includes an ISI correction stage for generating a partial result approximating intersymbol interference and comparing the partial result to a threshold, a carry look-ahead stage for generating a second partial result based in part on previously generated partial results, and a decision feedback stage for generating a final decision based on previous branches. Mode control multiplexers can select from PAM-2 and PAM-4 operating modes, PAM-2 and MAP-4 inputs at various stages, or from single-bit PAM-2 and two-bit PAM-4 outputs. ISI correction can additionally be reformulated to incorporate comparing raw input symbols to a combination of approximated ISI and a threshold.

Abstract translation: 用于SerDes接收机的N路并行，展开的判决反馈均衡器可以在四抽头PAM-2和二抽头PAM-4模式之间进行转换，通过使用模式控制多路复用器最大化硬件。 N个交错并行分支中的每一个包括用于产生近似符号间干扰的部分结果和将部分结果与阈值进行比较的ISI校正级，部分地基于先前产生的部分结果来生成第二部分结果的进位预测级，以及 用于根据先前分支产生最终决定的决策反馈阶段。 模式控制多路复用器可以从PAM-2和PAM-4操作模式，PAM-2和MAP-4输入在各个阶段，或单位PAM-2和两位PAM-4输出中进行选择。 ISI校正可以另外被重新配置，以将原始输入符号与近似ISI和阈值的组合进行比较。

公开(公告)号：US20150234423A1

公开(公告)日：2015-08-20

申请号：US14222157

申请日：2014-03-21

Applicant: LSI Corporation

Inventor： Volodymyr Shvydun ,  Adam B. Healey ,  Chaitanya Palusa ,  Hiep T. Pham

IPC: G06F1/12

CPC classification number: G06F1/12 ,  H03L7/087 ,  H03L7/091 ,  H04L7/0338 ,  H04L25/022 ,  H04L27/066 ,  H04L27/2275 ,  H04L27/2695 ,  H04L2027/0067

Abstract: Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.

Abstract translation: 公开了不需要错误锁存器或接收的输入数据的过采样的相位检测器和定时恢复技术。 相位检测方法包括将输入信号分离成N个连续数据位; 比较N个连续数据比特中的至少两个连续数据比特; 估计每个N个连续数据比特的数据比特值; 以及基于由N个连续数据位的数据位值形成的数据位模式和在N个连续数据位中的至少两个连续数据位的比较来确定相位差。

公开(公告)号：US20140146867A1

公开(公告)日：2014-05-29

申请号：US13685993

申请日：2012-11-27

Applicant: LSI CORPORATION

Inventor： Volodymyr Shvydun ,  Tomasz Prokop

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03057

Abstract: Described embodiments apply equalization to an input signal to a receiver such as a serial-deserializer. The receiver has an analog-to-digital converter (ADC), an M-way parallelizer, N serial buffers, N prefix buffers, and N decision feedback equalizers (DFEs), where M and N are greater than one. The ADC digitizes the input signal to form digitized symbols. The parallelizer assembles the digitized symbols into parallel sets of M digitized symbols. Each serial buffer has slots of M locations per slot and stores one set of M digitized symbols in one of the slots. The DFEs are responsive to common tap weight coefficients and produce parallel sets of M recovered data bits. Each DFE is first trained using sets of past digitized symbols loaded into a corresponding one of the prefix buffers and then processes digitized symbols stored in a corresponding one of the serial buffers.

Abstract translation: 所描述的实施例将均衡化到诸如串行解串器之类的接收器的输入信号。 接收机具有模数转换器（ADC），M路并行器，N个串行缓冲器，N个前缀缓冲器和N个判决反馈均衡器（DFE），其中M和N大于1。 ADC将输入信号数字化，形成数字化符号。 并行化器将数字化符号组装成M个数字化符号的并行集合。 每个串行缓冲器具有每个时隙的M个位置的时隙，并且在一个时隙中存储一组M个数字化符号。 DFE响应于公共抽头权重系数并产生M个恢复数据位的并行集合。 首先使用加载到相应的前缀缓冲器中的过去数字化符号的集合训练每个DFE，然后处理存储在对应的一个串行缓冲器中的数字化符号。

公开(公告)号：US09385893B2

公开(公告)日：2016-07-05

申请号：US14176728

申请日：2014-02-10

Applicant: LSI Corporation

Inventor： Chaitanya Palusa ,  Tomasz Prokop ,  Hiep T. Pham ,  Volodymyr Shvydun ,  Adam B. Healey

IPC: H04B1/38 ,  H04L5/16 ,  H04L27/10 ,  H04L27/18 ,  H04L25/03 ,  H04L7/00 ,  H04L27/00 ,  H04L7/02 ,  H03M1/12 ,  H03M1/38

CPC classification number: H04L25/03057 ,  H03M1/1215 ,  H03M1/38 ,  H04L7/0087 ,  H04L7/02 ,  H04L25/03 ,  H04L27/0002

Abstract: Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.

Abstract translation: 公开了模块化的低功率串行器 - 解串器接收器和用于配置这种接收器的方法。 所公开的接收机被配置为利用基于多个相移时钟信号时间交织的多个跟踪和保持电路来采样前端的输入信号。 所公开的接收机也是模块化的，并且基于确定的通信信道长度有选择地使用包括模拟前端和均衡器的各种处理组件，从超短距离应用到非常短的范围，中等到达，长距离和额外的 长期应用。

公开(公告)号：US09215106B2

公开(公告)日：2015-12-15

申请号：US14221968

申请日：2014-03-21

Applicant: LSI Corporation

Inventor： Chaitanya Palusa ,  Adam B. Healey ,  Hiep T. Pham ,  Volodymyr Shvydun

IPC: H04L25/03 ,  H03M1/00 ,  H04L1/06

CPC classification number: H04L25/03057 ,  H03H2218/06 ,  H03M1/00 ,  H03M1/14 ,  H03M2201/4135 ,  H04L1/06

Abstract: A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.

Abstract translation: 公开了一种用于校正码间干扰的多级系统和方法。 该系统包括被配置为对输入信号进行采样以产生第一组估计数据位的第一估计模块。 该系统还包括第二估计模块，其被配置为对由预定相移单元移位的输入信号相位进行采样以产生第二组估计数据位，其中第二组估计数据位至少部分地基于第一组产生 的估计数据位和至少一个前置标准系数。

公开(公告)号：US09130797B1

公开(公告)日：2015-09-08

申请号：US14267568

申请日：2014-05-01

Applicant: LSI Corporation

Inventor： Chaitanya Palusa ,  Volodymyr Shvydun ,  Hiep T. Pham ,  Adam B. Healey

IPC: H04B1/38 ,  H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/03146

Abstract: An interleaved track-and-hold front-end with multiphase clocks computes and propagates unrolled decision feedback equalization results along a pipeline with the final outputs selected from one of the interleaved previous output bits with a multiplexer operating over multiple unit intervals instead of one unit interval. An n-way interleaved serializer/deserializer utilizes an n unit interval multiplexer or n one unit interval multiplexers. Pipelined decision feedback equalization allows multiple, slower multiplexers.

Abstract translation: 具有多相时钟的交错跟踪和保持前端计算并沿着流水线传播展开的判决反馈均衡结果，其中最终输出从交织的先前输出位之一中选择，多路复用器以多个单位间隔工作，而不是一个单位间隔 。 n路交错串行器/解串器利用n单位间隔多路复用器或n个单位间隔多路复用器。 流水线判决反馈均衡允许多个较慢的多路复用器。