Invention Grant
- Patent Title: Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance
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Application No.: US14635288Application Date: 2015-03-02
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Publication No.: US09356131B2Publication Date: 2016-05-31
- Inventor: Manoj Mehrotra , Hiroaki Niimi
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank D. Cimino
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/49 ; H01L29/78 ; H01L21/28 ; H01L29/423 ; H01L29/51 ; H01L29/66 ; H01L29/06
Abstract:
The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.
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