Invention Grant
US09368194B2 Semiconductor integrated circuit device and system with memory cell array
有权
具有存储单元阵列的半导体集成电路器件和系统
- Patent Title: Semiconductor integrated circuit device and system with memory cell array
- Patent Title (中): 具有存储单元阵列的半导体集成电路器件和系统
-
Application No.: US14692566Application Date: 2015-04-21
-
Publication No.: US09368194B2Publication Date: 2016-06-14
- Inventor: Shigenobu Komatsu , Masanao Yamaoka , Noriaki Maeda , Masao Morimoto , Yasuhisa Shimazaki , Yasuyuki Okuma , Toshiaki Sano
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2009-211335 20090914
- Main IPC: G11C11/413
- IPC: G11C11/413 ; G11C11/417 ; G11C5/06 ; G11C5/14 ; H01L27/092 ; H01L27/11

Abstract:
A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.
Public/Granted literature
- US20150228330A1 Semicondutor Integrated Circuit Device and System Public/Granted day:2015-08-13
Information query
IPC分类: