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    Semiconductor Device
    1.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20150102421A1

    公开(公告)日：2015-04-16

    申请号：US14579898

    申请日：2014-12-22

    Applicant: Renesas Electronics Corporation

    Inventor： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

    IPC: H01L27/11 ,  G06F17/50

    CPC classification number: H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

    Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

    Abstract translation: 一种具有SRAM的半导体器件，包括：第一晶体管和第五晶体管设置在其中的单片第一有源区; 与第一有源区分离的第二有源区，其中设置第二晶体管; 其中设置第三晶体管和第六晶体管的单片第三有源区; 以及与第三有源区分离的第四有源区，其中设置第四晶体管。 每个驱动晶体管分为第一晶体管和第二晶体管（或第三晶体管和第四晶体管），并且这些驱动晶体管设置在不同的有源区域上。

    Multiport memory, memory macro and semiconductor device
    2.
    发明授权
    Multiport memory, memory macro and semiconductor device 有权

    公开(公告)号：US10460795B2

    公开(公告)日：2019-10-29

    申请号：US16214220

    申请日：2018-12-10

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii ,  Makoto Yabuuchi ,  Masao Morimoto

    IPC: G11C11/00 ,  G11C11/419 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418 ,  G11C8/08 ,  G11C8/06

    Abstract: A semiconductor device includes a latch circuit receiving a first signal, generated in synchronization with a clock signal, from a pulse generation circuit, and generating a second signal; a first delay circuit receiving the second signal from the latch circuit, and generating a third signal by delaying the second signal; a second delay circuit receiving the third signal from the first delay circuit, and generating a fourth signal by delaying the third signal; and a logic circuit receiving the second and fourth signals from the latch and second delay circuits, respectively, and generating a word line control signal based on one of the second signal and the fourth signal. The latch circuit generates the second signal of a first level based on the first signal, and generates the second signal of a second level, which is different from the first level, based on the third signal.

    Semicondutor integrated circuit device and system
    6.
    发明授权
    Semicondutor integrated circuit device and system 有权
    半导体集成电路器件及系统

    公开(公告)号：US09053975B2

    公开(公告)日：2015-06-09

    申请号：US14490461

    申请日：2014-09-18

    Applicant: Renesas Electronics Corporation

    Inventor： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

    IPC: G11C11/00 ,  H01L27/11 ,  H01L27/092

    CPC classification number: G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

    Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

    Abstract translation: 提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。 半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。 多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。 具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。 一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。 一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

    Semiconductor Device
    9.
    发明申请
    Semiconductor Device 有权

    公开(公告)号：US20160043091A1

    公开(公告)日：2016-02-11

    申请号：US14921038

    申请日：2015-10-23

    Applicant: Renesas Electronics Corporation

    Inventor： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

    IPC: H01L27/11 ,  H01L27/02

    CPC classification number: H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

    Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

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