Invention Grant
- Patent Title: Deadlock-avoiding coherent system on chip interconnect
- Patent Title (中): 死锁避免相干系统片上互连
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Application No.: US14059732Application Date: 2013-10-22
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Publication No.: US09372808B2Publication Date: 2016-06-21
- Inventor: Matthew D Pierson , Daniel B Wu , Kai Chirca
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frank D. Cimino
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/10 ; G06F13/16 ; H04L29/06 ; G06F13/42 ; G06F13/28 ; G06F13/40

Abstract:
This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked behind coherent requests. This invention also repartitions the master initiated traffic to move cache evictions (both with and without data) and non-coherent writes to the new non-blocking channel. This non-blocking pipeline removes the need for any coherent requests to complete before the snoop request can reach the memory controller. Repartitioning cache initiated evictions to the non-blocking pipeline prevents deadlock when snoop and eviction occur concurrently. The non-blocking channel of this invention combines snoop responses from memory controller initiated requests and master initiated evictions/non-coherent writes.
Public/Granted literature
- US20140115272A1 Deadlock-Avoiding Coherent System On Chip Interconnect Public/Granted day:2014-04-24
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