Invention Grant
US09379010B2 Methods for forming interconnect layers having tight pitch interconnect structures
有权
用于形成具有紧密间距互连结构的互连层的方法
- Patent Title: Methods for forming interconnect layers having tight pitch interconnect structures
- Patent Title (中): 用于形成具有紧密间距互连结构的互连层的方法
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Application No.: US14163323Application Date: 2014-01-24
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Publication No.: US09379010B2Publication Date: 2016-06-28
- Inventor: Christopher J. Jezewski , Jasmeet S. Chawla , Kanwal Jit Singh , Alan M. Myers , Elliot N. Tan , Richard E. Schenker
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532

Abstract:
Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.
Public/Granted literature
- US20150214094A1 METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCONNECT STRUCTURES Public/Granted day:2015-07-30
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