Invention Grant
- Patent Title: Method of joining a chip on a substrate
- Patent Title (中): 将芯片连接在基板上的方法
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Application No.: US12551960Application Date: 2009-09-01
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Publication No.: US09393633B2Publication Date: 2016-07-19
- Inventor: Pascal P Blais , Paul F Fortier , Kang-Wook Lee , Jae-Woong Nah , Soojae Park , Robert L Toutant , Alain A Warren
- Applicant: Pascal P Blais , Paul F Fortier , Kang-Wook Lee , Jae-Woong Nah , Soojae Park , Robert L Toutant , Alain A Warren
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully Scott Murphy and Presser
- Main IPC: B23K20/00
- IPC: B23K20/00 ; B23K1/00 ; H01L21/56 ; H01L23/00

Abstract:
A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
Public/Granted literature
- US20110049221A1 METHOD OF JOINING A CHIP ON A SUBSTRATE Public/Granted day:2011-03-03
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