公开(公告)号：US20110049221A1

公开(公告)日：2011-03-03

申请号：US12551960

申请日：2009-09-01

申请人： Pascal P. Blais ,  Paul F. Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L. Toutant ,  Alain A. Warren

发明人： Pascal P. Blais ,  Paul F. Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L. Toutant ,  Alain A. Warren

IPC分类号： B23K37/04 ,  B23K31/00

CPC分类号： B23K1/0016 ,  H01L21/563 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/75704 ,  H01L2224/75985 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/01026 ,  H01L2924/00

摘要： A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

摘要翻译： 公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。 该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。 减少弯曲和翘曲防止或减少超低k电介质的开裂和分层。

公开(公告)号：US20120292375A1

公开(公告)日：2012-11-22

申请号：US13566467

申请日：2012-08-03

申请人： Pascal P. Blais ,  Paul F. Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L. Toutant ,  Alain A. Warren

发明人： Pascal P. Blais ,  Paul F. Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L. Toutant ,  Alain A. Warren

IPC分类号： B23K37/04

CPC分类号： B23K1/0016 ,  H01L21/563 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/75704 ,  H01L2224/75985 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/01026 ,  H01L2924/00

摘要： A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

摘要翻译： 公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。 该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。 减小的弯曲和翘曲防止或减少超低k电介质的开裂和分层。

公开(公告)号：US09393633B2

公开(公告)日：2016-07-19

申请号：US12551960

申请日：2009-09-01

申请人： Pascal P Blais ,  Paul F Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L Toutant ,  Alain A Warren

发明人： Pascal P Blais ,  Paul F Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L Toutant ,  Alain A Warren

IPC分类号： B23K20/00 ,  B23K1/00 ,  H01L21/56 ,  H01L23/00

CPC分类号： B23K1/0016 ,  H01L21/563 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/75704 ,  H01L2224/75985 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/01026 ,  H01L2924/00

摘要： A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

摘要翻译： 公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。 该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。 减少弯曲和翘曲防止或减少超低k电介质的开裂和分层。

公开(公告)号：US09808874B2

公开(公告)日：2017-11-07

申请号：US13613000

申请日：2012-09-13

申请人： Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

发明人： Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

IPC分类号： B23K1/00 ,  B23K35/36 ,  B23K35/362

CPC分类号： B23K1/0016 ,  B23K35/3601 ,  B23K35/362

摘要： The present invention is directed to a soldering method for joining objects is also provided, comprising the steps of applying a flux composition to at least a portion of one or more of the objects, and joining the objects.

公开(公告)号：US09579738B2

公开(公告)日：2017-02-28

申请号：US13034932

申请日：2011-02-25

申请人： Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

发明人： Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

IPC分类号： B23K1/00 ,  B23K35/36 ,  B23K35/362

CPC分类号： B23K1/0016 ,  B23K35/3601 ,  B23K35/362

摘要： The present invention is directed to flux compositions. One composition comprises an activator, a medium-viscosity solvent being a polymer, and a high-viscosity solvent being a copolymer containing first monomers and second monomers. Another composition comprises an activator, and a high-viscosity solvent comprising a copolymer containing first monomers and second monomers. Another composition comprises an activator of 6-12 percent by weight of glutaric acid, pimelic acid, tartaric acid, or mixtures thereof, and a medium-viscosity solvent of 88-94 percent by weight comprising a polymer with hydroxyl end groups. Another composition comprises an activator in a liquid state comprising poly(ethylene glycol)-diacid, and a medium-viscosity solvent comprising a polymer with hydroxyl end groups.

摘要翻译： 本发明涉及助焊剂组合物。 一种组合物包含活化剂，中等粘度溶剂为聚合物，高粘度溶剂为包含第一单体和第二单体的共聚物。 另一组合物包含活化剂和包含含有第一单体和第二单体的共聚物的高粘度溶剂。 另一组合物包含6-12重量％的戊二酸，庚二酸，酒石酸或其混合物的活化剂和88-94重量％的中等粘度溶剂，其包含具有羟基端基的聚合物。 另一种组合物包含液态的活化剂，其包含聚（乙二醇） - 二酸，以及包含具有羟基端基的聚合物的中等粘度溶剂。

公开(公告)号：US20120217289A1

公开(公告)日：2012-08-30

申请号：US13034932

申请日：2011-02-25

申请人： Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

发明人： Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

IPC分类号： B23K35/363 ,  B23K1/20

CPC分类号： B23K1/0016 ,  B23K35/3601 ,  B23K35/362

摘要： The present invention is directed to flux compositions and uses thereof. One composition comprises an activator, a medium-viscosity solvent being a polymer, and a high-viscosity solvent being a copolymer containing first monomers and second monomers. Another composition comprises an activator, and a high-viscosity solvent comprising a copolymer containing first monomers and second monomers. Another composition comprises an activator of 6-12 percent by weight of glutaric acid, pimelic acid, tartaric acid, or mixtures thereof, and a medium-viscosity solvent of 88-94 percent by weight comprising a polymer with hydroxyl end groups. Another composition comprises an activator in a liquid state comprising poly(ethylene glycol)-diacid, and a medium-viscosity solvent comprising a polymer with hydroxyl end groups. A soldering method for joining objects is also provided, comprising the steps of applying a flux composition to at least a portion of one or more of the objects, and joining the objects.

摘要翻译： 本发明涉及助焊剂组合物及其用途。 一种组合物包含活化剂，中等粘度溶剂为聚合物，高粘度溶剂为包含第一单体和第二单体的共聚物。 另一组合物包含活化剂和包含含有第一单体和第二单体的共聚物的高粘度溶剂。 另一组合物包含6-12重量％的戊二酸，庚二酸，酒石酸或其混合物的活化剂和88-94重量％的中等粘度溶剂，其包含具有羟基端基的聚合物。 另一种组合物包含液态的活化剂，其包含聚（乙二醇） - 二酸，以及包含具有羟基端基的聚合物的中等粘度溶剂。 还提供了一种用于接合物体的焊接方法，包括以下步骤：将焊剂组合物施加到一个或多个物体的至少一部分，并且连接物体。

公开(公告)号：US20130001279A1

公开(公告)日：2013-01-03

申请号：US13613000

申请日：2012-09-13

申请人： Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

发明人： Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

IPC分类号： B23K31/02

CPC分类号： B23K1/0016 ,  B23K35/3601 ,  B23K35/362

摘要： The present invention is directed to a soldering method for joining objects is also provided, comprising the steps of applying a flux composition to at least a portion of one or more of the objects, and joining the objects.

摘要翻译： 本发明还涉及一种用于接合物体的焊接方法，其包括以下步骤：将焊剂组合物施加到一个或多个物体的至少一部分上并连接物体。

公开(公告)号：US09273408B2

公开(公告)日：2016-03-01

申请号：US13612812

申请日：2012-09-12

申请人： Bing Dang ,  Michael A. Gaynes ,  Paul A. Lauro ,  Jae-Woong Nah

发明人： Bing Dang ,  Michael A. Gaynes ,  Paul A. Lauro ,  Jae-Woong Nah

IPC分类号： B23K1/20 ,  C25D5/02 ,  H01L21/02 ,  H01L23/00 ,  C25D7/12 ,  H05K3/34

CPC分类号： H01L24/11 ,  C25D5/022 ,  C25D7/123 ,  H01L21/02107 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/11001 ,  H01L2224/11002 ,  H01L2224/11312 ,  H01L2224/1141 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1162 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K2201/10734 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01026 ,  H01L2924/00

摘要： Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned mask layer. Solder is injected over the pillars or BLM, filling the channels. Molten solder can be injected in cavities formed in round wafers without leakage using a carrier assembly that accommodates wafers that have been previously subjected to mask layer deposition and patterning. One such carrier assembly includes an elastomeric body portion having a round recess, the walls of the recess forming a tight seal with the round wafer. Other carrier assemblies employ adhesives applied around the peripheral edges of the wafers to ensure sealing between the carrier assemblies and wafers.

摘要翻译： 通过使用注射成型焊料在圆形晶片上提供焊料凸块。 在图案化掩模层的通道内的I / O焊盘上形成铜柱或极限极限冶金。 焊料注入柱子或BLM，填充通道。 可以使用容纳预先经过掩模层沉积和图案化的晶片的载体组件将熔融的焊料注入到圆形晶片形成的空腔中而不发生泄漏。 一个这样的载体组件包括具有圆形凹部的弹性体主体部分，凹部的壁与圆形晶片形成紧密密封。 其他载体组件使用施加在晶片的周边边缘周围的粘合剂，以确保载体组件和晶片之间的密封。

公开(公告)号：US20150147846A1

公开(公告)日：2015-05-28

申请号：US14525069

申请日：2014-10-27

申请人： Claudius FEGER ,  Michael A. Gaynes ,  Jae-Woong Nah ,  Da-Yuan Shih

发明人： Claudius FEGER ,  Michael A. Gaynes ,  Jae-Woong Nah ,  Da-Yuan Shih

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L21/463 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/92 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1605 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2741 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83

摘要： A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures. In another embodiment the height of the chip soldering structures is greater than the height of the substrate soldering structures and the pre-applied underfill is contiguous with the semiconductor chip and sufficiently thick so as to extend substantially no further than the full height of the chip soldering structures. A process comprises manufacturing semiconductor assemblies from these devices by soldering the chip and the substrate to one another

摘要翻译： 预组装半导体器件包括半导体芯片上的芯片焊接结构和对应于芯片焊接结构的衬底上的衬底焊接结构。 衬底焊接结构朝着芯片焊接结构延伸，以形成与芯片焊接结构的焊接连接。 芯片和衬底相对于彼此处于预组装位置。 基板焊接结构的高度大于芯片焊接结构的高度。 预先施加的底部填充物与基底相邻并且足够厚以便基本上不超过基底焊接结构的全高度延伸。 在另一个实施例中，芯片焊接结构的高度大于衬底焊接结构的高度，并且预先施加的底部填充物与半导体芯片邻接并且足够厚以便基本上不超过芯片焊接的全部高度 结构。 一种方法包括通过将芯片和衬底彼此焊接来从这些器件制造半导体组件

公开(公告)号：US08870051B2

公开(公告)日：2014-10-28

申请号：US13463412

申请日：2012-05-03

申请人： Peter J. Brofman ,  Jae-Woong Nah ,  Katsuyuki Sakuma

发明人： Peter J. Brofman ,  Jae-Woong Nah ,  Katsuyuki Sakuma

IPC分类号： B23K37/04

CPC分类号： B23K31/02 ,  B23K1/0016 ,  B23K3/047 ,  B23K35/0222 ,  B23K37/04 ,  B23K2101/40 ,  H01L24/81 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/15787 ,  H01L2924/00

摘要： A flip chip assembly apparatus includes at least one warpage-suppressor assembly. Each warpage-suppressor assembly can include a side heater, a deformable material pad, and an actuator assembly for moving the side heater and the deformable material pad. Each side heater provides additional heat to peripheral solder balls during bonding of two substrates, thereby facilitating the reflow of the peripheral solder balls. Each deformable material pad contacts, and presses down on, a surface of one of the two substrates under bonding. The deformable material pad(s) can prevent or minimize warpage of the contacted substrate.

摘要翻译： 倒装芯片组装装置包括至少一个翘曲抑制组件。 每个翘曲抑制组件可以包括侧加热器，可变形材料垫和用于移动侧加热器和可变形材料垫的致动器组件。 每个侧面加热器在两个基板的接合期间向外围焊球提供额外的热量，从而便于外围焊球的回流。 每个可变形材料焊盘在粘合下接触并压下两个基板之一的表面。 可变形材料垫可以防止或最小化接触的基底的翘曲。