Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.