公开(公告)号：US09965014B2

公开(公告)日：2018-05-08

申请号：US14129920

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Min Yeol Lim ,  Robert P Knight ,  Gautam Upadhyaya ,  Neha Sharma

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3203

Abstract: Various embodiments are generally directed to generating logs recording events related to wakelocks at application and kernel levels, and then temporally aligning graphs of those events in a visual presentation to enable debugging of wakelocks. An apparatus to debug wakelocks includes a processor component; a capture component to intercept calls associated with application level wakelocks, the intercepted calls received by an application power manager of an operating system from application routines; and a relaying component to cooperate with the application power manager to provide indications of the intercepted calls to a system log generator of the operating system coupled to the application power manager, the system log generator to generate system log data comprising indications of events associated with execution of the operating system by the processor component and the indications of the intercepted calls. Other embodiments are described and claimed.

公开(公告)号：US20160328002A1

公开(公告)日：2016-11-10

申请号：US15214030

申请日：2016-07-19

Applicant: Intel Corporation

Inventor： Robert P. Knight ,  Gautam Upadhyaya ,  Min Yeol Lim ,  Neha Sharma

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3206 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/152

Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

公开(公告)号：US09395788B2

公开(公告)日：2016-07-19

申请号：US14228784

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Robert P. Knight ,  Gautam Upadhyaya ,  Min Yeol Lim ,  Neha Sharma

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3206 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/152

Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

Abstract translation: 用于分析计算设备的处理器的功率状态转换的技术，包括由计算设备确定由计算设备的处理器输入的功率状态和基于功率状态记录输入的功率状态的持续时间，其中功率状态记录 包括指示计算设备的处理器在功率状态之间的转变的转换数据。 计算设备还基于所输入的确定的功率状态和用于处理器的目标驻留数据来确定计算设备的处理器的功率状态选择的精度。 目标驻留数据针对处理器的多个功率状态的每个功率状态识别导致功率守恒的相应功率状态所需的时间量。

公开(公告)号：US10067551B2

公开(公告)日：2018-09-04

申请号：US15214030

申请日：2016-07-19

Applicant: Intel Corporation

Inventor： Robert P. Knight ,  Gautam Upadhyaya ,  Min Yeol Lim ,  Neha Sharma

IPC: G06F1/26 ,  G06F1/32

Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.