发明授权
US09419095B2 Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process
有权
最后一个进程中的伪栅极的制造方法和栅极最后工艺中的虚拟栅极的制造方法
- 专利标题: Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process
- 专利标题(中): 最后一个进程中的伪栅极的制造方法和栅极最后工艺中的虚拟栅极的制造方法
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申请号: US14119864申请日: 2012-12-12
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公开(公告)号: US09419095B2公开(公告)日: 2016-08-16
- 发明人: Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
- 申请人: Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
- 申请人地址: CN Beijing
- 专利权人: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
- 当前专利权人: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
- 当前专利权人地址: CN Beijing
- 代理机构: Goodwin
- 优先权: CN201210509428 20121203
- 国际申请: PCT/CN2012/086397 WO 20121212
- 国际公布: WO2014/086052 WO 20140612
- 主分类号: H01L21/338
- IPC分类号: H01L21/338 ; H01L29/66 ; H01L29/423 ; H01L29/51 ; H01L21/28
摘要:
A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.