Invention Grant
US09431274B2 Method for reducing underfill filler settling in integrated circuit packages
有权
降低集成电路封装中底部填充物沉降的方法
- Patent Title: Method for reducing underfill filler settling in integrated circuit packages
- Patent Title (中): 降低集成电路封装中底部填充物沉降的方法
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Application No.: US13722886Application Date: 2012-12-20
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Publication No.: US09431274B2Publication Date: 2016-08-30
- Inventor: Suriyakala Ramalingam , Manish Dubey , Hsin-Yu Li , Michelle S. Phen , Hitesh Arora , Nisha Ananthakrishnan , Yiqun Bai , Yonghao Xiu , Rajendra C. Dias
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/56 ; H01L23/00 ; H01L23/29

Abstract:
Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20140177149A1 REDUCTION OF UNDERFILL FILLER SETTLING IN INTEGRATED CIRCUIT PACKAGES Public/Granted day:2014-06-26
Information query
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