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    METHODS TO PREVENT FILLER ENTRAPMENT IN MICROELECTRONIC DEVICE TO MICROELECTRONIC SUBSTRATE INTERCONNECTION STRUCTURES
    1.
    发明申请
    METHODS TO PREVENT FILLER ENTRAPMENT IN MICROELECTRONIC DEVICE TO MICROELECTRONIC SUBSTRATE INTERCONNECTION STRUCTURES 审中-公开
    防止微电子器件填充微电子基板互连结构的方法

    公开(公告)号：US20150179479A1

    公开(公告)日：2015-06-25

    申请号：US14638328

    申请日：2015-03-04

    Applicant: INTEL CORPORATION

    Inventor： Manish Dubey ,  Rajendra C. Dias ,  Yonghao Xiu ,  Arjun Krishnan ,  Yiqun Bai ,  Purushothan Kaushik Muthur Srinath

    IPC: H01L21/56

    CPC classification number: H01L21/563 ,  H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

    Abstract translation: 本说明书的实施例包括在微电子器件上处理底部填充材料之后将微电子器件附着到具有互连结构的微电子衬底的方法，其中，在将微电子器件连接到微电子器件之前，底部填充材料内的填料颗粒可能被排除离开互连结构 器件到微电子结构。 这些方法可以包括在互连结构上引入电荷，并且可以包括将互连结构放置在相对的板之间，并且在将底部填充材料沉积在互连结构上之后在相对的板之间产生偏压。

    Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures
    3.
    发明授权
    Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures 有权
    防止填料在微电子器件中捕获到微电子衬底互连结构的方法

    公开(公告)号：US08999765B2

    公开(公告)日：2015-04-07

    申请号：US13925967

    申请日：2013-06-25

    Applicant: Intel Corporation

    Inventor： Manish Dubey ,  Rajendra C. Dias ,  Yonghao Xiu ,  Arjun Krishnan ,  Yiqun Bai ,  Purushotham Kaushik Muthur Srinath

    IPC: H01L23/488 ,  H01L21/56

    CPC classification number: H01L21/563 ,  H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

    Abstract translation: 本说明书的实施例包括在微电子器件上处理底部填充材料之后，将微电子器件附着到具有互连结构的微电子衬底的方法，其中在将微电子器件连接到底部填充材料之前，底部填充材料内的填料颗粒可能被排除离开互连结构 器件到微电子结构。 这些方法可以包括在互连结构上引入电荷，并且可以包括将互连结构放置在相对的板之间，并且在将底部填充材料沉积在互连结构上之后在相对的板之间产生偏压。

    REDUCTION OF UNDERFILL FILLER SETTLING IN INTEGRATED CIRCUIT PACKAGES
    5.
    发明申请
    REDUCTION OF UNDERFILL FILLER SETTLING IN INTEGRATED CIRCUIT PACKAGES 审中-公开
    减少集成电路封装中的填充填料

    公开(公告)号：US20160343591A1

    公开(公告)日：2016-11-24

    申请号：US15225678

    申请日：2016-08-01

    Applicant: INTEL CORPORATION

    Inventor： Suriyakala Ramalingam ,  Manish Dubey ,  Hsin-Yu Li ,  Michelle S. Phen-Givoni ,  Hitesh Arora ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Yonghao Xiu ,  Rajendra C. Dias

    IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29

    Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例涉及用于具有以通常随机分布图案排列的填充颗粒的底部填充层的集成电路（IC）封装的技术和配置。 在一些实施例中，通过对IC封装组件的一个或多个部件上的静电电荷，通过对填料进行表面处理以减少填充剂电荷，可以通过施加电力来抵抗填料颗粒的大致随机分布图案 通过使用相对较低的最大填充剂粒度的底部填充材料和/或通过在相对低的温度下快速固化底部填充层，使底部填充材料的填料颗粒在与重力方向相反的方向上。 可以描述和/或要求保护其他实施例。

    Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures
    9.
    发明授权
    Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures 有权
    防止填料在微电子器件中捕获到微电子衬底互连结构的方法

    公开(公告)号：US09230833B2

    公开(公告)日：2016-01-05

    申请号：US14638328

    申请日：2015-03-04

    Applicant: INTEL CORPORATION

    Inventor： Manish Dubey ,  Rajendra C. Dias ,  Yonghao Xiu ,  Arjun Krishnan ,  Yiqun Bai ,  Purushotham Kaushik Muthur Srinath

    IPC: H01L21/56 ,  H01L23/00

    CPC classification number: H01L21/563 ,  H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

    Abstract translation: 本说明书的实施例包括在微电子器件上处理底部填充材料之后将微电子器件附着到具有互连结构的微电子衬底的方法，其中，在将微电子器件连接到微电子器件之前，底部填充材料内的填料颗粒可能被排除离开互连结构 器件到微电子结构。 这些方法可以包括在互连结构上引入电荷，并且可以包括将互连结构放置在相对的板之间，并且在将底部填充材料沉积在互连结构上之后在相对的板之间产生偏压。

    PROCESSES AND METHODS FOR APPLYING UNDERFILL TO SINGULATED DIE
    10.
    发明申请
    PROCESSES AND METHODS FOR APPLYING UNDERFILL TO SINGULATED DIE 审中-公开

    公开(公告)号：US20180286704A1

    公开(公告)日：2018-10-04

    申请号：US15477053

    申请日：2017-04-01

    Applicant: Intel Corporation

    Inventor： Elizabeth M. Nofen ,  Arjun Krishnan ,  James C. Matayabas, JR. ,  Venmathy McMahan ,  Nisha Ananthakrishnan ,  Yonghao Xiu

    IPC: H01L21/56 ,  H01L21/66 ,  H01L21/67 ,  H01L21/782 ,  H01L21/82

    Abstract: A process for applying an underfill material to a die is disclosed. A wafer is diced into a plurality of dies (without having any underfill film thereon) such that the dies have exposed bumps prior to an underfill process. Thus, the dies can be tested about their bump-sides because the bumps are entirely exposed for testing. The dies are then reconstituted bump-side up on a carrier panel in an array such that the dies are separated from each other by a gap. Underfill material (e.g., epoxy flux film) is then vacuum laminated to the carrier panel and the plurality of dies to encapsulate the dies. The underfill material is then cut between adjacent dies such that a portion of the underfill material covers at least one side edge of each die. The encapsulated dies are then removed from the carrier panel, thereby being prepared for a thermal bonding process to a substrate. Associated devices are provided.

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