公开(公告)号：US10229887B2

公开(公告)日：2019-03-12

申请号：US15087270

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Mitul B. Modi

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/285 ,  H01L23/31 ,  H01L21/78 ,  H01L23/544 ,  H01L21/784 ,  H01L23/29 ,  H01L21/683 ,  H01L21/56

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.

公开(公告)号：US20180226358A1

公开(公告)日：2018-08-09

申请号：US15945023

申请日：2018-04-04

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Anna M. Prakash ,  Joshua D. Heppner ,  Eric J. Li ,  Nachiket R. Raravikar

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

公开(公告)号：US09704811B1

公开(公告)日：2017-07-11

申请号：US14978294

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Joshua D Heppner ,  Mitul B Modi ,  Anna M. Prakash

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/60 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49524 ,  H01L23/552 ,  H01L24/27 ,  H01L24/33 ,  H01L2224/97 ,  H01L2924/3025

Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.

公开(公告)号：US20160343591A1

公开(公告)日：2016-11-24

申请号：US15225678

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Suriyakala Ramalingam ,  Manish Dubey ,  Hsin-Yu Li ,  Michelle S. Phen-Givoni ,  Hitesh Arora ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Yonghao Xiu ,  Rajendra C. Dias

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于具有以通常随机分布图案排列的填充颗粒的底部填充层的集成电路（IC）封装的技术和配置。 在一些实施例中，通过对IC封装组件的一个或多个部件上的静电电荷，通过对填料进行表面处理以减少填充剂电荷，可以通过施加电力来抵抗填料颗粒的大致随机分布图案 通过使用相对较低的最大填充剂粒度的底部填充材料和/或通过在相对低的温度下快速固化底部填充层，使底部填充材料的填料颗粒在与重力方向相反的方向上。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10206277B2

公开(公告)日：2019-02-12

申请号：US14975162

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Manish Dubey ,  Tatyana N. Andryushchenko ,  Aleksandar Aleksov ,  David W. Staines

IPC: H05K1/00 ,  H05K1/02 ,  A41D1/00 ,  A43B3/00 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for gradient encapsulant protection of devices in stretchable electronic. For instance, in accordance with one embodiment, there is an apparatus with an electrical device on a stretchable substrate; one or more stretchable electrical interconnects coupled with the electrical device; one or more electrical components electrically coupled with the electrical device via the one or more stretchable electrical interconnects; and a gradient encapsulating material layered over and fully surrounding the electrical device and at least a portion of the one or more stretchable electrical interconnects coupled thereto, in which the gradient encapsulating material has an elastic modulus greater than the stretchable substrate and in which the elastic modulus of the gradient encapsulating material is less than the electrical device. Other related embodiments are disclosed.

公开(公告)号：US10192810B2

公开(公告)日：2019-01-29

申请号：US13930082

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Rajendra C. Dias ,  Edvin Cetegen ,  Lars D. Skoglund

IPC: H01L23/22 ,  H01L23/24 ,  H01L23/485 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

公开(公告)号：US09953929B2

公开(公告)日：2018-04-24

申请号：US15074050

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Anna M. Prakash ,  Joshua D. Heppner ,  Eric J. Li ,  Nachiket R. Raravikar

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

公开(公告)号：US20170250145A1

公开(公告)日：2017-08-31

申请号：US15595581

申请日：2017-05-15

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Joshua D. Heppner ,  Mitul B. Modi ,  Anna M. Prakash

IPC: H01L23/60 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49524 ,  H01L23/552 ,  H01L24/27 ,  H01L24/33 ,  H01L2224/97 ,  H01L2924/3025

Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.

公开(公告)号：US09721906B2

公开(公告)日：2017-08-01

申请号：US14841052

申请日：2015-08-31

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Baris Bicen ,  Digvijay Raorane ,  Bharat P. Penmecha

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/3142 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/83801 ,  H01L2924/1511 ,  H01L2924/1515 ,  H01L2924/3511

Abstract: An electronic package that includes a substrate and a die attached to the substrate. A plurality of supports attached to the substrate adjacent to the die. At least one support in the plurality of supports is positioned adjacent to at least one corner of the die such that the at least one corner of the die is positioned adjacent to the at least one support. Other example forms relate to a method of fabricating an electronic package. The method includes securing a die to a substrate and securing a plurality of supports to the substrate such that at least one support is adjacent to at least one corner of the die.

公开(公告)号：US09591758B2

公开(公告)日：2017-03-07

申请号：US14227805

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Aleksandar Aleks Aleksov ,  Mauro Kobrinsky ,  Johanna Swan ,  Rajendra C. Dias

IPC: H05K1/00 ,  H05K1/14 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/85399 ,  H01L2924/00014 ,  H05K1/0284 ,  H05K1/0393 ,  H05K1/117 ,  H05K1/142 ,  H05K1/148 ,  H05K3/4691 ,  H05K2201/10287 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.

Abstract translation: 这里通常讨论的是可以包括用于柔性线接合装置的装置，系统或方法的系统和装置。 根据一个实例，设备可以包括（1）第一刚性电路，其包括靠近第一刚性电路的第一边缘的第一多个接合焊盘，（2）第二刚性电路，其包括接近于第一刚性电路的第二多个接合焊盘 第二刚性电路的第一边缘，与第一刚性电路相邻的第二刚性电路和面向第一刚性电路的第一边缘的第二刚性电路的第一边缘，或（3）第一多个引线接合线， 所述第一多个引线接合线的接合线电和机械地连接到所述第一多个接合焊盘的接合焊盘和所述第二多个接合焊盘的接合焊盘。