REDUCTION OF UNDERFILL FILLER SETTLING IN INTEGRATED CIRCUIT PACKAGES
    2.
    发明申请
    REDUCTION OF UNDERFILL FILLER SETTLING IN INTEGRATED CIRCUIT PACKAGES 审中-公开
    减少集成电路封装中的填充填料

    公开(公告)号:US20160343591A1

    公开(公告)日:2016-11-24

    申请号:US15225678

    申请日:2016-08-01

    申请人: INTEL CORPORATION

    IPC分类号: H01L21/56 H01L23/00 H01L23/29

    摘要: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

    摘要翻译: 本公开的实施例涉及用于具有以通常随机分布图案排列的填充颗粒的底部填充层的集成电路(IC)封装的技术和配置。 在一些实施例中,通过对IC封装组件的一个或多个部件上的静电电荷,通过对填料进行表面处理以减少填充剂电荷,可以通过施加电力来抵抗填料颗粒的大致随机分布图案 通过使用相对较低的最大填充剂粒度的底部填充材料和/或通过在相对低的温度下快速固化底部填充层,使底部填充材料的填料颗粒在与重力方向相反的方向上。 可以描述和/或要求保护其他实施例。