Invention Grant
- Patent Title: Pulsed laser anneal process for transistors with partial melt of a raised source-drain
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Application No.: US14667544Application Date: 2015-03-24
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Publication No.: US09443980B2Publication Date: 2016-09-13
- Inventor: Jacob Jensen , Tahir Ghani , Mark Y. Liu , Harold Kennel , Robert James
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/268 ; H01L29/66 ; H01L21/265 ; H01L29/08 ; H01L29/10 ; H01L29/165 ; H01L29/417

Abstract:
A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.
Public/Granted literature
- US20150200301A1 PULSED LASER ANNEAL PROCESS FOR TRANSISTORS WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN Public/Granted day:2015-07-16
Information query
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