公开(公告)号：US10170314B2

公开(公告)日：2019-01-01

申请号：US15246468

申请日：2016-08-24

Applicant: Intel Corporation

Inventor： Jacob Jensen ,  Tahir Ghani ,  Mark Y. Liu ,  Harold Kennel ,  Robert James

IPC: H01L21/268 ,  H01L29/417 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L21/324

Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

公开(公告)号：US09443980B2

公开(公告)日：2016-09-13

申请号：US14667544

申请日：2015-03-24

Applicant: Intel Corporation

Inventor： Jacob Jensen ,  Tahir Ghani ,  Mark Y. Liu ,  Harold Kennel ,  Robert James

IPC: H01L29/78 ,  H01L21/268 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

公开(公告)号：US20150200301A1

公开(公告)日：2015-07-16

申请号：US14667544

申请日：2015-03-24

Applicant: Intel Corporation

Inventor： Jacob Jensen ,  Tahir GHANI ,  Mark Y. LIU ,  Harold KENNEL ,  Robert JAMES

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

Abstract translation: 一种非平面晶体管，其包括设置在半导体鳍片的相对端上的部分熔融的凸起半导体源极/漏极，其间设置有栅极堆叠。 升高的半导体源极/漏极包括在熔体深度之上的超激活掺杂剂区域和低于熔体深度的活化掺杂剂区域。 超活化掺杂剂区域具有比活化的掺杂剂区域更高的活化掺杂剂浓度和/或具有在整个熔融区域中恒定的活化的掺杂剂浓度。 翅片形成在基板上，并且半导体材料或半导体材料堆叠沉积在设置在沟道区域的相对侧上的翅片的区域上以形成升高的源极/漏极。 进行脉冲激光退火以仅将融化的半导体材料的一部分熔化在熔体深度之上。