Invention Grant
- Patent Title: Digital phase locked loop for low jitter applications
- Patent Title (中): 用于低抖动应用的数字锁相环
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Application No.: US14245374Application Date: 2014-04-04
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Publication No.: US09455728B2Publication Date: 2016-09-27
- Inventor: Jingdong Deng , Chung S. Ho , David Flye , Zhenrong Jin , Ramana M. Malladi
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran Cole & Calderon P.C.
- Agent Steven Meyers; Andrew M. Calderon
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/099 ; H03L7/087 ; G06F17/50

Abstract:
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
Public/Granted literature
- US20150288370A1 DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS Public/Granted day:2015-10-08
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