Invention Grant
- Patent Title: Methods and structures for protecting one area while processing another area on a chip
-
Application No.: US14487213Application Date: 2014-09-16
-
Publication No.: US09472402B2Publication Date: 2016-10-18
- Inventor: Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy J. Dalton , Katherina E. Babich , Arpan P. Mohorowala , Harald Okorn-Schmidt
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Thompson Hine LLP
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/027 ; H01L21/311 ; G03F7/11

Abstract:
Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
Public/Granted literature
- US20150004802A1 Methods and Structures for Protecting One Area While Processing Another Area on a Chip Public/Granted day:2015-01-01
Information query
IPC分类: