公开(公告)号：US09431523B2

公开(公告)日：2016-08-30

申请号：US14156489

申请日：2014-01-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/66818

Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

Abstract translation: 在半导体散热片上形成栅极结构之后，在形成凸起的有源区之前，使用定向离子束在半导体鳍片的端壁上形成与半导体鳍片的长度方向垂直的绝缘材料部分。 方向离子束的角度选择为包括半导体鳍片的长度方向的垂直平面，从而避免在半导体鳍片的纵向侧壁上形成电介质材料部分。 执行半导体材料的选择性外延以从半导体鳍片的侧壁表面生长凸起的有源区域。 可选地，可以在选择性外延工艺之前去除电介质材料部分的水平部分。 此外，可以在选择性外延工艺之后任选地去除电介质材料部分。

公开(公告)号：US09418903B2

公开(公告)日：2016-08-16

申请号：US14283633

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl Radens

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/308 ,  H01L21/3083 ,  H01L27/1211 ,  H01L29/66818

Abstract: Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction of a fractional effective device width, thereby allowing greater flexibility for design applications, such as SRAM design optimization. A portion of some fins are clad with a capping layer or workfunction material to change the threshold voltage (Vt) for a part of the fin, rendering that part of the fin electrically inactive, which changes the effective device width (Weff). Other fins are unclad, and provide maximum area of constant threshold voltage. In this way, the effective device width of some devices is reduced. Therefore, the effective device width is controllable by controlling the level of cladding of the fin.

Abstract translation: 本发明的实施例提供了通过引入分数有效装置宽度可以放宽有效宽度的固有离散化的方法和结构，从而为诸如SRAM设计优化的设计应用提供了更大的灵活性。 一些翅片的一部分用覆盖层或功函材料包覆以改变鳍的一部分的阈值电压（Vt），使得该部分鳍电活动，这改变了有效器件宽度（Weff）。 其他翅片不包括，并提供最大面积的恒定阈值电压。 以这种方式，某些设备的有效设备宽度就会降低。 因此，通过控制翅片的包层水平来控制有效的装置宽度。

公开(公告)号：US20160218222A1

公开(公告)日：2016-07-28

申请号：US15089647

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7887 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/306 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7881

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

公开(公告)号：US09660105B2

公开(公告)日：2017-05-23

申请号：US15089647

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L21/336 ,  H01L21/311 ,  H01L29/788 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L27/12 ,  H01L27/115 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7887 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/306 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7881

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

公开(公告)号：US09305930B2

公开(公告)日：2016-04-05

申请号：US14102843

申请日：2013-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L27/12 ,  H01L21/336

CPC classification number: H01L29/7887 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/306 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7881

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

Abstract translation: 提供了一种双鳍单浮栅配置的闪存器件。 半导体翅片形成在背栅导体层和背栅电介质层的堆叠上。 在阵列环境中形成一对半导体散热片，使得能够沿阵列内的半导体鳍片的长度方向形成浅沟槽隔离结构。 在半导体鳍片的侧壁上形成隧道电介质之后，通过沉积保形导电材料层和各向同性蚀刻，在每对靠近近端的半导体鳍片之间形成浮栅电极。 通过介电层和导电材料层的沉积和图案化来形成控制栅极电介质和控制栅电极。

公开(公告)号：US20160359038A1

公开(公告)日：2016-12-08

申请号：US15238884

申请日：2016-08-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/66818

Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

公开(公告)号：US09349730B2

公开(公告)日：2016-05-24

申请号：US13945415

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Ajey Poovannummoottil Jacob ,  Kangguo Cheng ,  Bruce B. Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Ramachandra Divakaruni

IPC: H01L21/20 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了由这些方法形成的方法和半导体结构，其有助于制造半导体鳍结构。 所述方法包括例如：提供具有在衬底上延伸的至少一个半导体鳍片的晶片; 将所述半导体鳍片的一部分转换成隔离层，所述隔离层将所述半导体鳍片的半导体层与所述衬底分离; 并且在半导体鳍片的第一鳍片区域中形成第一结构类型的翅片装置，并且在半导体鳍片的第二鳍片区域中形成第二结构类型的鳍片装置（ s），其中第一架构类型和第二架构类型是不同的fin设备架构。

公开(公告)号：US09093496B2

公开(公告)日：2015-07-28

申请号：US13945445

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Ajey P. Jacob ,  Kangguo Cheng ,  Bruce B. Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Ramachandra Divakaruni

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/088 ,  H01L27/105 ,  H01L29/78 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L21/302

CPC classification number: H01L21/76243 ,  H01L21/302 ,  H01L21/76267 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L27/1211 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供半导体制造方法，其包括通过以下方式制造半导体鳍片结构：提供具有在衬底上延伸的至少一个翅片的晶片，所述至少一个鳍片包括设置在第二层上方的第一层; 机械稳定第一层; 去除所述翅片的所述第二层的至少一部分以在所述第一层下面形成空隙; 至少部分地用隔离材料填充第一层下面的空隙，以在散热片内产生隔离层; 并且在翅片的第一翅片区域中形成第一结构类型的翅片装置，并且在翅片的第二翅片区域中形成第二结构类型的翅片装置， ，其中第一种架构类型和第二种架构类型是不同的鳍设备架构。

公开(公告)号：US09960168B2

公开(公告)日：2018-05-01

申请号：US14582655

申请日：2014-12-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Benjamin Ryan Cipriany ,  Ramachandra Divakaruni ,  Brian J. Greene ,  Ali Khakifirooz ,  Byeong Yeol Kim ,  William Larsen Nicoll

IPC: H01L21/20 ,  H01L27/108 ,  H01L21/324 ,  H01L21/84 ,  H01L29/94 ,  H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L27/10829 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/945

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

公开(公告)号：US09524986B2

公开(公告)日：2016-12-20

申请号：US14315362

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Ramachandra Divakaruni ,  Judson R. Holt ,  Arvind Kumar ,  Unoh Kwon

IPC: H01L21/02 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L21/306 ,  H01L21/311 ,  H01L29/16 ,  H01L21/3105

CPC classification number: H01L27/1207 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.

Abstract translation: 本发明一般涉及半导体器件，更具体地说，涉及通过捕获外延期间发生的晶格位错而在绝缘体上硅绝缘体（SOI）衬底上形成高迁移率鳍状场效应晶体管（finFET）鳍的结构和方法 在半导体层中形成的凹部中生长。 结晶晶格位错可以保留在薄的隔离层下方，从而减少器件厚度以及高纵横比蚀刻和鳍形成的需要。