Invention Grant
- Patent Title: Methods of forming under device interconnect structures
- Patent Title (中): 在器件互连结构下形成的方法
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Application No.: US13798575Application Date: 2013-03-13
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Publication No.: US09490201B2Publication Date: 2016-11-08
- Inventor: Patrick Morrow , Don Nelson , M. Clair Webb , Kimin Jun , Il-Seok Son
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/20 ; H01L23/00 ; H01L23/535 ; H01L21/74 ; H01L23/528
Abstract:
Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
Public/Granted literature
- US20140264739A1 METHODS OF FORMING UNDER DEVICE INTERCONNECT STRUCTURES Public/Granted day:2014-09-18
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