公开(公告)号：US10236282B2

公开(公告)日：2019-03-19

申请号：US15026268

申请日：2013-12-18

申请人： Intel Corporation

发明人： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Rajashree Baskaran ,  Paul B. Fischer

IPC分类号： H01L27/02 ,  H01L21/8258 ,  H01L21/683 ,  H01L23/528 ,  H01L29/16 ,  H01L29/20 ,  H01L27/085

摘要： An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.

公开(公告)号：US12100761B2

公开(公告)日：2024-09-24

申请号：US17578259

申请日：2022-01-18

申请人： Intel Corporation

发明人： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Donald W. Nelson

IPC分类号： H01L29/78 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L29/417 ,  H01L23/15

CPC分类号： H01L29/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/05 ,  H01L29/41791 ,  H01L23/145 ,  H01L23/15 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/16227

摘要： An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US20190326405A1

公开(公告)日：2019-10-24

申请号：US16457728

申请日：2019-06-28

申请人： Intel Corporation

发明人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

IPC分类号： H01L29/417 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

摘要： Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

公开(公告)号：US09721898B2

公开(公告)日：2017-08-01

申请号：US15285454

申请日：2016-10-04

申请人： Intel Corporation

发明人： Patrick Morrow ,  Don Nelson ,  M. Clair Webb ,  Kimin Jun ,  Il-Seok Son

IPC分类号： H01L23/535 ,  H01L21/20 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/74 ,  H01L23/50 ,  H01L27/12

CPC分类号： H01L23/535 ,  H01L21/2007 ,  H01L21/743 ,  H01L23/50 ,  H01L23/522 ,  H01L23/5286 ,  H01L24/18 ,  H01L27/1207

摘要： Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.

公开(公告)号：US12100762B2

公开(公告)日：2024-09-24

申请号：US17578847

申请日：2022-01-19

申请人： Intel Corporation

发明人： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Donald W. Nelson

IPC分类号： H01L29/78 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L29/417 ,  H01L23/15

CPC分类号： H01L29/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/05 ,  H01L29/41791 ,  H01L23/145 ,  H01L23/15 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/16227

摘要： An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US10797139B2

公开(公告)日：2020-10-06

申请号：US16457728

申请日：2019-06-28

申请人： Intel Corporation

发明人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

IPC分类号： H01L21/00 ,  H01L23/522 ,  H01L27/00 ,  H01L29/00 ,  H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324

摘要： Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

公开(公告)号：US09490201B2

公开(公告)日：2016-11-08

申请号：US13798575

申请日：2013-03-13

申请人： Intel Corporation

发明人： Patrick Morrow ,  Don Nelson ,  M. Clair Webb ,  Kimin Jun ,  Il-Seok Son

IPC分类号： H01L23/522 ,  H01L21/20 ,  H01L23/00 ,  H01L23/535 ,  H01L21/74 ,  H01L23/528

CPC分类号： H01L23/535 ,  H01L21/2007 ,  H01L21/743 ,  H01L23/50 ,  H01L23/522 ,  H01L23/5286 ,  H01L24/18 ,  H01L27/1207

摘要： Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.

摘要翻译： 描述了在器件结构下形成微电子互连的方法。 这些方法和结构可以包括在第一衬底中形成器件层，在第二衬底中形成至少一个布线层，然后将第一衬底与第二衬底耦合，其中第一衬底与第二衬底结合。

公开(公告)号：US11594452B2

公开(公告)日：2023-02-28

申请号：US17122939

申请日：2020-12-15

申请人： Intel Corporation

发明人： Il-Seok Son ,  Colin T. Carver ,  Paul B. Fischer ,  Patrick Morrow ,  Kimin Jun

IPC分类号： H01L21/768 ,  H01L21/304 ,  H01L21/84 ,  H01L21/306 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06

摘要： Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

公开(公告)号：US11264493B2

公开(公告)日：2022-03-01

申请号：US15747423

申请日：2015-09-25

申请人： Intel Corporation

发明人： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Donald W. Nelson

IPC分类号： H01L29/78 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L29/417 ,  H01L23/15

摘要： An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US10896847B2

公开(公告)日：2021-01-19

申请号：US16539957

申请日：2019-08-13

申请人： Intel Corporation

发明人： Il-Seok Son ,  Colin T. Carver ,  Paul B. Fischer ,  Patrick Morrow ,  Kimin Jun

IPC分类号： H01L21/768 ,  H01L21/304 ,  H01L21/84 ,  H01L21/306 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06

摘要： Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.